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參數(shù)資料
| 型號： | SAA2023 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | 戴納信貸驅(qū)動處理器的系統(tǒng) |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA2023 |
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May 1994
18
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
Table 15
Port expander outputs.
D0
TO
D3
When SAA2023 is used with SRAM these I/O pins form the lower nibble of the data bus connection to the RAM, and
should be connected to the corresponding data I/O pins of the SRAM. When SAA2023 is used with DRAM these
input/output pins are the data lines for the RAM, they should be connected directly to the DRAM data I/O pins.
D4
TO
D7
These input/output pins are the upper nibble of the data bus for use with SRAM, and when SRAM is being used they
should be connected directly to the corresponding SRAM I/O pins.
PIN NAME
PIN
PORT EXPANDER
OUTPUT
CONDITIONS
QFP80
TQFP80
A14/PINO1
A13/PINO2
A16/PINO3
A15/PINO4
A12/PINO5
46
50
47
48
45
44
48
45
46
43
PINO1
PINO2
PINO3
PINO4
PINO5
RType = 00
RType = 00
RType = 00 or RType = 01
RType = 00 or RType = 01
RType = 00
Fig.10 DRAM read cycle timing.
handbook, full pagewidth
A0 to A8
OEN
A10/RAS
D0 to D3
A9/CAS
tRP
tRAS
tASR
tRAH
MGB386
tRCD
tOEZ
tOFF
tCAS
tCP
tCAH
tCAC
tRAC
tASC
NIBBLE 0 DATA
NIBBLE 1 DATA
NIBBLE 2 DATA
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
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