參數(shù)資料
型號： SAA2023
廠商： NXP Semiconductors N.V.
英文描述： Drive processor for DCC systems
中文描述： 戴納信貸驅動處理器的系統(tǒng)
文件頁數(shù)： 31/56頁
文件大?。?/td> 274K
代理商： SAA2023
May 1994
31
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
V
DD7
This is the supply pin for the output buffers to the data lines
of the system RAM. It should always be connected
externally. Decouple this pin with a 22 nF capacitor to the
V
SS7
pin.
V
SS7
This is the ground supply pin for the output buffers of the
data lines of the system RAM. This pin is connected
internally to all the supply ground pins (V
SS1
to V
SS6
),
however it should always be connected externally.
Auxiliary envelope detection
INTMASK
INTMASK is a interrupt mask register. This register sets
the mode of operation for the interrupt interface, and is
writable only.
Table 22
Interrupt mask register.
Notes
1.
2.
3.
4.
5.
6.
Vup
≡
rising edge of VIRGIN interrupt.
AEup
≡
rising edge of AUX envelope interrupt.
AEdn
≡
falling edge of AUX envelope interrupt.
Lup
≡
rising edge of LABEL interrupt.
Ldn
≡
falling edge of LABEL interrupt.
ECZ
≡
AUX envelope counter has just reached zero interrupt.
BIT
7
6
5
4
3
2
1
0
Meaning
Default
BP1
0
BP0
0
Vup
(1)
0
AEup
(2)
0
AEdn
(3)
0
Lup
(4)
0
Ldn
(5)
0
ECZ
(6)
0
BP1
AND
BP0 (
BYPASS
)
If any of the bypass bits are HIGH then the interrupts are
not passed on to the microcontroller, instead the level of
the corresponding signal is available an the interrupt pin.
Table 23
BP1 and BP0.
Notes
1.
LAB = LABEL (HIGH if a LABEL condition is detected
in the envelope of the AUX channel).
AENV = envelope of the AUX channel (1 bit binary).
VIR = VIRGIN (indicated by the total [continuous]
absence of signal on the AUX channel).
2.
3.
BP
EFFECT OF BYPASS
1
0
0
0
1
1
0
1
0
1
no bypass
LAB on L3INT pin; note 1
AENV on L3INT pin; note 2
VIR on L3INT pin; note 3
The AUX envelope information is only valid when the
digital equalizer is in search mode and when the tape
speed is between the values of
3 to 48
×
nominal tape speed. The timing relationships
between the AUX channel input signal, AENV, LAB and
VIR are shown in Figs 26 to 28. The delays t
d1
and t
d2
are
between 0.25 and 0.5t
AUX
(AUX envelope periods). The
delays t
d3
, t
d4
, t
d5
and t
d6
are between 2 and 6t
AUX
(AUX envelope periods).
When using the digital equalizer in search mode first
program the digital equalizer to search mode, then
program the INTMASK register.
MASK
If the BP1 and BP0 bits are LOW then the mask bits take
effect. Any combination of the mask bits may be HIGH,
enabling the corresponding interrupts. The interrupt pin
L3INT is active LOW when used for interrupts and active
HIGH when used for bypassing. So if it is not in bypass
mode and at least one of the interrupts has occurred it will
go LOW and stays LOW until DEQ status byte 0 has been
read. Extra interrupts that occur after the first interrupt and
before the DEQ status byte 0 is read are seen in the status
register. Extra interrupts that occur after the status byte
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