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參數(shù)資料
| 型號(hào)： | SAA2023 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | 戴納信貸驅(qū)動(dòng)處理器的系統(tǒng) |
| 文件頁數(shù)： | 37/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA2023 |
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May 1994
37
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
CLKSET
Table 38
CLKSET clock extraction settings.
Note
1.
LEAE (leakage enable): this setting enables a leakage function in the PLL clock extraction loop filter. This gives a
slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance. For
home (static) applications program this bit to logic 1 and for portable applications to logic 0.
BIT
7
6
5
4
3
2
1
0
Meaning
Default
LEAE
(1)
FR1
0
FR0
0
GNOR
1
GE1
1
GE0
0
RD1
1
RD0
0
1
Table 39
FR1 and FR0 clock extraction frequency range
control.
Note that in the (FR = 0) range the clock extraction stays
in its normal range only, hence it does not enter the
extended range.
Figure 30 shows the lock characteristic of the clock
extraction PLL.
FR
EFFECT ON PLL FREQUENCY
LOOP
1
0
0
0
1
1
0
1
0
1
range
±
8%
range
±
16%
range
±
22%
range
±
28%
Table 40
GNOR gain in normal frequency range mode of
clock extraction.
Table 41
GE1 and GE0 gain in extended frequency
range mode of clock extraction.
GNOR
EFFECT ON GAIN IN NORMAL RANGE
0
1
gain 2; for portable (mobile) applications
gain 1; for home (static) applications
GE
EFFECT ON PLL GAIN IN EXTENDED
RANGE
1
0
0
0
1
1
0
1
0
1
gain 2
gain 3
gain 4
gain 5; do not use
Fig.30 Clock extraction PLL lock characteristic.
handbook, full pagewidth
30
20
10
0
10
4
MGB404
10
3
10
2
f (Hz)
bit rate
deviation
(%)
8% frequency loop range limitation
16% frequency loop range limitation
22% frequency loop range limitation
28% frequency loop range limitation
(3)
(2)
(1)
(1) Gain 4.
(2) Gain 3.
(3) Gain 2.
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