參數(shù)資料
型號: S71WS512NE0BFWZZ3
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA96
封裝: 9 X 12 MM, LEAD FREE, FBGA-96
文件頁數(shù): 107/142頁
文件大小: 1996K
代理商: S71WS512NE0BFWZZ3
June 28, 2004 S71WS512NE0BFWZZ_00_A1
128Mb pSRAM
107
P r e l i m i n a r y
FUNCTIONAL DESCRIPTION (Continued)
Burst Read Termination
Burst read operation can be terminated by CE#1 brought to High. If BL is set on
Continuous, burst read operation is continued endless unless terminated by
CE#1=H. It is inhibited to terminate burst read before first data out is completed.
In order to guarantee last data output, the specified minimum value of CE#1=L
hold time from clock edge must be satisfied. After termination, the specified
minimum recovery time is required to start new access.
Burst Write Termination
Burst write operation can be terminated by CE#1 brought to High. If BL is set on
Continuous, burst write operation is continued endless unless terminated by
CE#1=H. It is inhibited to terminate burst write before first data in is completed.
In order to guarantee last write data being latched, the specified minimum values
of CE#1=L hold time from clock edge must be satisfied. After termination, the
specified minimum recovery time is required to start new access.
ADDRESS
ADV#
DQ
OE#
CLK
Valid
CE#1
WAIT#
Q
1
Q
2
t
OHZ
t
AC
t
CKQX
t
CKCLH
t
TRB
t
CKOH
t
CHZ
High-Z
ADDRESS
ADV#
DQ
WE#
CLK
Valid
CE#1
WAIT#
t
CKCLH
t
TRB
t
CKWH
t
CHZ
High-Z
D
2
D
1
t
DHCK
t
DHCK
t
D-
t
D-
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