參數(shù)資料
型號: S71WS512NE0BFWZZ3
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA96
封裝: 9 X 12 MM, LEAD FREE, FBGA-96
文件頁數(shù): 103/142頁
文件大小: 1996K
代理商: S71WS512NE0BFWZZ3
June 28, 2004 S71WS512NE0BFWZZ_00_A1
128Mb pSRAM
103
P r e l i m i n a r y
FUNCTIONAL DESCRIPTION (Continued)
Latency
Read Latency (RL) is the number of clock cycles between the address being latched
and first read data becoming available during synchronous burst read operation.
It is set through CR Set sequence after power-up. Once specific RL is set through
CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1. The
burst operation is always started after fixed latency with respect to Read Latency
set in CR.
ADDRESS
ADV#
CLK
Valid
Q1
Q2
Q3
D1
D2
D3
D4
0
1
2
3
4
5
RL=3
Q4
D5
DQ [Out]
DQ [In]
CE#1
OE# or WE#
WAIT#
WAIT#
6
Q5
D5
Q1
Q2
D1
D2
D3
RL=4
Q3
D4
DQ [Out]
DQ [In]
WAIT#
WAIT#
Q4
D5
Q1
D1
D2
RL=5
Q2
D3
DQ [Out]
DQ [In]
WAIT#
WAIT#
Q3
D4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
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S71WS512NA0BFEZZ2 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512NA0BFEZZ3 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512NA0BFIZZ0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512NA0BFIZZ2 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512NA0BFIZZ3 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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