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參數(shù)資料
| 型號： | S71WS512NE0BFWZZ0 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA96 |
| 封裝： | 9 X 12 MM, LEAD FREE, FBGA-96 |
| 文件頁數(shù)： | 50/142頁 |
| 文件大小： | 1996K |
| 代理商： | S71WS512NE0BFWZZ0 |
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50
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
synchronous mode. The configuration register can not be changed during device
operations (program, erase, or sector lock).
Read Configuration Register Command Sequence
The configuration register can be read with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be C6h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be read out of the data bus with the address bus set to
address 000h. Once the data has been read from the configuration register, a
software reset command is required to set the device into the correct state.
Read Mode Setting
This setting allows the system to enable or disable burst mode during system op-
erations.
Configuration Bit CR15
determines this setting: “1’ for asynchronous
mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock
cycles that must elapse after AVD# is driven active before data will be available.
This value is determined by the input frequency of the device.
Configuration Bit
CR13–CR11
determine the setting (see
Table 13
).
The wait state command sequence instructs the device to set a particular number
of clock cycles for the initial access in burst mode. The number of wait states that
should be programmed into the device is directly related to the clock frequency.
Figure 1. Synchronous/Asynchronous State Diagram
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(D15 = 1)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512NE0BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NE0BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512P | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Migrating from the S71WS512N to the S71WS512P |
| S71WS512PC0HF3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM |
| S71WS512PC0HF3HL0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM |
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