- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄365460 > S71WS512NC0BFWE72 (Spansion Inc.) Stacked Multi-Chip Product (MCP) PDF資料下載
參數(shù)資料
| 型號(hào)： | S71WS512NC0BFWE72 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁(yè)數(shù)： | 100/188頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BFWE72 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)當(dāng)前第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)
98
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
16 Commonly Used Terms
Term
Definition
ACC
ACCelerate.
A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above V
CC
. In some devices ACC
may protect all sectors when at a low voltage.
A
max
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
A
min
Least significant bit of the address input signals (A0 for all devices in this document).
Asynchronous
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Autoselect
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Boot sector
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boundary
Location at the beginning or end of series of memory locations.
Burst Read
See
synchronous read
.
Byte
8 bits
CFI
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
Clear
Zero (Logic Low Level)
Configuration Register
Special purpose register which must be programmed to enable synchronous read
mode
Continuous Read
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Erase Suspend/Erase Resume
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
BGA
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
Linear Read
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
or without wraparound before requiring a new initial address
.
MCP
Multi-Chip Package. A method of combining integrated circuits in a single package by
stacking
multiple die of the same or different devices.
Memory Array
The programmable area of the product available for data storage.
MirrorBit Technology
Spansion trademarked technology for storing multiple bits of data in the same
transistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71WS512NC0BFWE73 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY20 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY22 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY23 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY30 | Stacked Multi-Chip Product (MCP) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512NC0BFWE73 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWEJ0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWEJ2 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWEJ3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWEK0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。