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參數(shù)資料
| 型號(hào)： | S71WS512NA0BFWZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 104/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512NA0BFWZZ2 |
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104
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
FUNCTIONAL DESCRIPTION (Continued)
Address Latch by ADV#
The ADV# indicates valid address presence on address inputs. During synchronous
burst read/write operation mode, all the address are determined on the positive
edge of ADV# when CE#1=L. The specified minimum value of ADV#=L setup
time and hold time against valid edge of clock where RL count begin must be
satisfied for appropriate RL counts. Valid address must be determined with
specified setup time against either the negative edge of ADV# or negative edge
of CE#1 whichever comes late. And the determined valid address must not be
changed during ADV#=L period.
Burst Length
Burst Length is the number of word to be read or write during synchronous burst
8, 16 words boundary or continuous for entire address through CR Set sequence.
The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from initial address being latched, device internal address
counter assign +1 to the previous address until reaching the end of boundary
address and then wrap round to least significant address (=0). After completing
read data out or write data latch for the set burst length, operation automatically
ended except for continuous burst length. When continuous burst length is set,
read/write is endless unless it is terminated by the positive edge of CE#1.
Single Write
Single Write is synchronous write operation with Burst Length =1. The device can
be configured either to "Burst Read & Single Write" or to "Burst Read & Burst
Write" through CR set sequence. Once the device is configured to "Burst Read &
Single Write" mode, the burst length for syncronous write operation is always
fixed 1 regardless of BL values set in CR, while burst length for read is in accordance
with BL values set in CR.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512NA0BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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