- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192306 > S71PL129JC0BFW9Z2 (SPANSION LLC) Stacked Multi-Chip Product (MCP) Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | S71PL129JC0BFW9Z2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 96/153頁 |
| 文件大?。?/td> | 3651K |
| 代理商： | S71PL129JC0BFW9Z2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當(dāng)前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
45
Advance
Informatio n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 12 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in
PL129J), whichever happens later. All data is latched on the rising edge of WE#
or CE# (CE1# / CE2# in PL129J), whichever happens first. See AC Characteristics
for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See “Erase Suspend/Erase Re-
sume Commands” on page 50 for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See “Reset Command,” for more
information.
tions” for more information. The AC Characteristics table provides the read
parameters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL129NC0HFW4U3 | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| S71PL191HB0BFI100 | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| S71VS128RC0ZHK203 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71VS128RC0ZHK2L2 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71WS512ND0BAWEH | SPECIALTY MEMORY CIRCUIT, PBGA84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL129JC0BFW9Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129N | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128兆位(16/8/8米x16位元)的CMOS 3.0電壓只有同時(shí)讀/寫,頁面模式閃存 |
| S71PL129NB0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
| S71PL129NB0HAW5B0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
| S71PL129NB0HAW5B2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。