- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192306 > S71PL129JC0BFW9Z2 (SPANSION LLC) Stacked Multi-Chip Product (MCP) Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | S71PL129JC0BFW9Z2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64 |
| 文件頁(yè)數(shù)： | 47/153頁(yè) |
| 文件大?。?/td> | 3651K |
| 代理商： | S71PL129JC0BFW9Z2 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)當(dāng)前第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
138
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
Advance
Info rmation
AC Characteristics
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please
contact local Spansion representative for the relaxation of 1s limitation.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
tWC
70
1000
65
1000
65
1000
ns
1,2
Address Setup Time
tAS
0—0—0—
ns
3
CE1# Write Pulse Width
tCW
45
—
40
—
40
—
ns
3
WE# Write Pulse Width
tWP
45
—
40
—
40
—
ns
3
LB#/UB# Write Pulse Width
tBW
45
—
40
—
40
—
ns
3
LB#/UB# Byte Mask Setup Time
tBS
-5
—
–5
—
–5
—
ns
4
LB#/UB# Byte Mask Hold Time
tBH
-5
—
–5
—
–5
—
ns
5
Write Recovery Time
tWR
0—0—0—
ns
6
CE1# High Pulse Width
tCP
10
—
12
—
12
—
ns
WE# High Pulse Width
tWHP
7.5
1000
7.5
1000
7.5
1000
ns
7
LB#/UB# High Pulse Width
tBHP
10
1000
12
1000
12
1000
ns
Data Setup Time
tDS
15
—
12
—
12
—
ns
Data Hold Time
tDH
0—0—0—
ns
tOHCL
-5
—
–5
—
–5
—
ns
8
OE# High to Address Setup Time for Write
tOES
0—0—0—
ns
9
LB# and UB# Write Pulse Overlap
tBWO
30
—
30
—
30
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL129NC0HFW4U3 | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| S71PL191HB0BFI100 | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| S71VS128RC0ZHK203 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71VS128RC0ZHK2L2 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71WS512ND0BAWEH | SPECIALTY MEMORY CIRCUIT, PBGA84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL129JC0BFW9Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129N | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128兆位(16/8/8米x16位元)的CMOS 3.0電壓只有同時(shí)讀/寫(xiě),頁(yè)面模式閃存 |
| S71PL129NB0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
| S71PL129NB0HAW5B0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
| S71PL129NB0HAW5B2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit MCPs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。