參數(shù)資料
型號(hào)： S71PL129JC0BFW9Z2
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA64
封裝： 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64
文件頁數(shù)： 41/153頁
文件大小： 3651K
代理商： S71PL129JC0BFW9Z2
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
133
Advance
Informatio n
Functional Description
Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of 1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
3. Can be either VIL or VIH but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the device in power-
down mode and maintains the low-power idle state as long as CE2 is kept Low. CE2 High resumes
the device from power-down mode. These devices have three power-down modes. These can be
programmed by series of read/write operation. Each mode has following features.
The default state is Sleep and it is the lowest power consumption but all data is lost once CE2 is
brought to Low for Power Down. It is not required to program to Sleep mode after power-up.
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between each read/write
operation requires that device be in standby mode. The following table shows the detail sequence.
Mode
CE2#
CE1#
WE#
OE#
LB#
UB#
A21-0
DQ8-1
DQ16-9
Standby (Deselect)
H
X
High-Z
Output Disable (Note 1)
HL
HH
X
Note 3
High-Z
Output Disable (No Read)
HL
H
Valid
High-Z
Read (Upper Byte)
H
L
Valid
High-Z
Output Valid
Read (Lower Byte)
L
H
Valid
Output Valid
High-Z
Read (Word)
L
Valid
Output Valid
No Write
LH
H
Valid
Invalid
Write (Upper Byte)
H
L
Valid
Invalid
Input Valid
Write (Lower Byte)
L
H
Valid
Input Valid
Invalid
Write (Word)
L
Valid
Input Valid
Power Down
L
XXXX
X
High-Z
32M
64M
Mode
Retention Data
Retention Address
Mode
Retention Data
Retention Address
Sleep (default)
No
N/A
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
Cycle #
Operation
Address
Data
1st
Read
3FFFFFh (MSB)
Read Data (RDa)
2nd
Write
3FFFFFh
RDa
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