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參數(shù)資料
| 型號： | S71PL129JC0BFW9Z2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 46/153頁 |
| 文件大小： | 3651K |
| 代理商： | S71PL129JC0BFW9Z2 |
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Publication Number S71PL129Jxx_00
Revision A Amendment 8 Issue Date October 28, 2005
ADVANCE
INFORMATION
S29PL129J for MCP
128 Megabit (8 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIOTM Control
Distinctive Characteristics
Architectural Advantages
128 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— CE#1 controlled banks:
Bank 1A:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
- 48Mbit (32Kw x 96)
— CE#2 controlled banks:
Bank 2A:
- 48 Mbit (32Kw x 96)
Bank 2B:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the VIO pin
Secured Silicon Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
Performance Characteristics
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 A typical standby mode current
Software Features
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
WP#/ ACC (Write Protect/Acceleration) input
—At VIL, hardware level protection for the first and
last two 4K word sectors.
—At VIH, allows removal of sector protection
—At VHH, provides accelerated programming in a
factory setting
Datasheet
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