參數(shù)資料
型號： S70WS512N00BFWAB3
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 8/93頁
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB3
6
S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005
A d v a n c e I n f o r m a t i o n
Figures
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 9.1
Figure 9.2
Figure 9.3
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Figure 12.10
Figure 12.11
Figure 12.12
Figure 12.13
Figure 12.14
Figure 12.15
Figure 12.16
Figure 12.17
Figure 12.18
Figure 12.19
Figure 12.20
Figure 12.21
Figure 12.22
Figure 12.23
Figure 12.24
Synchronous/Asynchronous State Diagram...........................................................................................23
Synchronous Read ............................................................................................................................26
Single Word Program.........................................................................................................................32
Write Buffer Programming Operation ...................................................................................................36
Sector Erase Operation ......................................................................................................................38
Write Operation Status Flowchart ........................................................................................................45
Advanced Sector Protection/Unprotection .............................................................................................51
PPB Program/Erase Algorithm .............................................................................................................54
Lock Register Program Algorithm.........................................................................................................57
Maximum Negative Overshoot Waveform .............................................................................................64
Maximum Positive Overshoot Waveform ...............................................................................................64
Test Setup .......................................................................................................................................65
Input Waveforms and Measurement Levels...........................................................................................65
V
CC
Power-up Diagram ......................................................................................................................66
CLK Characterization .........................................................................................................................68
CLK Synchronous Burst Mode Read......................................................................................................69
8-word Linear Burst with Wrap Around.................................................................................................70
8-word Linear Burst without Wrap Around ............................................................................................70
Linear Burst with RDY Set One Cycle Before Data ..................................................................................71
Asynchronous Mode Read...................................................................................................................72
Reset Timings...................................................................................................................................72
Chip/Sector Erase Operation Timings ...................................................................................................74
Asynchronous Program Operation Timings ............................................................................................75
Synchronous Program Operation Timings .............................................................................................76
Accelerated Unlock Bypass Programming Timing ...................................................................................76
Data# Polling Timings (During Embedded Algorithm) .............................................................................77
Toggle Bit Timings (During Embedded Algorithm) ..................................................................................77
Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................78
DQ2 vs. DQ6 ....................................................................................................................................78
Latency with Boundary Crossing when Frequency > 66 MHz....................................................................79
Latency with Boundary Crossing into Program/Erase Bank ......................................................................80
Example of Wait State Insertion..........................................................................................................81
Back-to-Back Read/Write Cycle Timings ...............................................................................................82
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