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參數(shù)資料
| 型號(hào)： | S5H1420 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Channel Decoder for DVB-S/DSS |
| 中文描述： | 頻道解碼器DVB-S/DSS |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 849K |
| 代理商： | S5H1420 |
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S5H1420
DBS Channel Decoder for DVB-S/DSS
-6
3. FUNCTIONAL DESCRIPTION
3.1 Signal processing
3.1.1 I and Q inputs
The dual ADC can get differential (IP/IN, QP/QN) or single inputs (IP, QP), I/Q signals from the tuner
are fed to the IP and QP inputs through a DC coupling capacitor and IN and QN must be set DC
voltage as CML (typical: 1/2VDD). The reference voltage of high [VREF-H] and low [VREF-L] should
be supplied from external generator for application flexibility.
3.1.2 PRE-AGC
The power of I/Q signal is compared to a programmable threshold value, and the difference is
integrated. This signal is then converted into a Pulse Width Modulation (PWM) signal to drive the AGC
output and it will be low pass filtered by a simple RC analog filter to control the gain command of any
amplifier before the A/D converter. The PWM output operates at
f
clk
/ (1, 4, 8 and 16) in order to
decrease the radiated noise and to simplify the filter design, and is a 5 V tolerant open drain stage.
The PRE-AGC Controls are in Address 0x07 and the PRE-AGC integrator register is in Address 0x15.
3.1.3 Root raised cosine and rate conversion filter
The Root raised cosine (RRC) and rate conversion filter performs anti-aliasing filtering, root raised
cosine shaping, rate conversion, timing synchronization and tracking with the timing loop.
Two roll-off factors are available: 0.35 (DVB-S) and 0.20 (DSS).
3.1.4 Offset cancellation
This device suppresses the residual I/Q DC component in the QPSK system control register in
Addresses 0x05 and 0x06.
3.1.5 POST-AGC
The POST-AGC shall be able to adjust the gain of the incoming I/Q sample from the RRC and rate
conversion filter and implement the closed loop that sets the gain adjustment. The reset value (0x8000)
of the POST-AGC integrator register can allow an initial settling time of less than 50k master clock
periods.
The POST-AGC Controls are in Address 0x08 and the POST-AGC integrator register is in Address
0x16.
3.2 Timing recovery
3.2.1 Timing control
The timing loop is programmed with the expected symbol frequency.
We have
δ
parameter, which determine one or two sampling method. It can be expressed as:
(1+
α
)
fsym >
clk
2
f
for
δ
=1.
In contrast,
(1+
α
)
fsym <
clk
2
f
for
δ
=2.
Where
α
is roll-off factor: 0.35 for DVB-S, 0.2 for DSS.
Thus
Timing NCO frequency word register setting is:
NCO frequency word =
sym
clk
f
f
2
24
δ
Samsung Electronics Co, Ltd. Proprietary Information
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5H1420X01 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Channel Decoder for DVB-S/DSS |
| S-5-H-16.4-D | 制造商:Interconnect Devices Inc (IDI) 功能描述:S-5-H-16.4-D S/C 制造商:Interconnect Devices Inc (IDI) 功能描述:PROBE |
| S-5-H-16.4-D S/C | 功能描述:觸點(diǎn)探頭 HEADED SERRATED RoHS:否 制造商:IDI 類型:Probes 尖端類型:Spherical Radius 長度:8.26 mm 電流額定值:10 A 彈力:2.3 oz 行程:1.52 mm 系列:101050 |
| S5H16.4G | 制造商:Interconnect Devices Inc (IDI) 功能描述:SPRING CONTACT PROBE PCB 制造商:Interconnect Devices Inc (IDI) 功能描述:SPRING CONTACT PROBE, PCB 制造商:Interconnect Devices Inc (IDI) 功能描述:SPRING CONTACT PROBE, PCB; Connector Type:Test Point; Connector Tip Style:Waffle; Current Rating:5A; Overall Length:36.07mm; Spring Force Initial:2.8oz; Spring Force Working Travel:16.4oz; Centerline Spacing:4.75mm; Length:1.420" ;RoHS Compliant: Yes |
| S-5-H-16.4-G | 制造商:Interconnect Devices Inc (IDI) 功能描述:GLD PLTD WAFFLE, SIZE 5, SPRING FORCE 8OZ@.170 TRAVEL, GLD PLT PLUNGER |
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