參數(shù)資料
型號: S5H1420
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Channel Decoder for DVB-S/DSS
中文描述: 頻道解碼器DVB-S/DSS
文件頁數(shù): 18/31頁
文件大?。?/td> 849K
代理商: S5H1420
S5H1420
DBS Channel Decoder for DVB-S/DSS
-18
QPSK control registers
(Address: 0x05 – 0x06)
Addr. RegName
Signal name
Width Property Description
KICK_EN
[7]
R/W
[1] PLL Kicker enable [0] Disable
[6]
R/W
Set to “0”
[5]
R/W
Set to “1”
DC offset remove
DC_EN
[4]
R/W
[1] Enable [0] Disable
[3]
R/W
Set to “1”
[2]
R/W
Set to “1”
QPSK operation mode
[1] 1 sampling/1 symbol
MODE
[1]
R/W
[0] 2 sampling/1 symbol
QPSK start signal
0x05
QPSK01
(0xBC)
Q_START
[0]
R/W
[1] Start [0] Idle
[7]
R/W
Set to “1”
[6]
R/W
Set to “1”
[5]
R/W
Set to “0”
[4]
R/W
Set to “0”
Dump phase loop filter & timing loop
filter accumulator
DUMP_ACC
[3]
R/W
[0 and then 1] The read operation enabled, when user set
DUMP_ACC “0” and then “1”.
0x06
QPSK02
(0xC1)
DC_WIN
[2:0]
R/W
Window position from MSB removing DC offset. Unsigned integer
(0
DC_WIN
7)
AGC control registers
(Address: 0x07 – 0x08)
Addr. RegName
Signal name
Width Property Description
PWM signal is reversed
[1] PWM signal active low
INV_PULSE
[7]
R/W
[0] PWM signal active high
[6]
R/W
Set to “0”
[5]
R/W
Set to “1”
0x07
Pre01
(0x30)
PRE_TH
[4:0]
R/W
PRE-AGC threshold
[7:6]
R/W
Set to “0”
0x08
Post01
(0x10)
POST_TH
[5:0]
R/W
POST-AGC threshold
Samsung Electronics Co, Ltd. Proprietary Information
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