參數(shù)資料
型號(hào)： S5H1420
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Channel Decoder for DVB-S/DSS
中文描述： 頻道解碼器DVB-S/DSS
文件頁數(shù)： 12/31頁
文件大小： 849K
代理商： S5H1420
S5H1420
DBS Channel Decoder for DVB-S/DSS
-12
3.4.9.3
MPEG Clock Control
-
Through Register Setting, S5H1420 can control MPEG CLOCK to MCU.
STB MCU
60MHz
81MHz
Symbol Rate
Symbol Rate
>= 25
Symbol Rate
< 25
Symbol Rate
>= 25
Symbol Rate
< 25
S5H1420 Master
Clock
Sampling
59MHz
88MHz
80MHz
88MHz
1
2
1
2
- Control register, 3-bit, uses Address 0x22 (
MPEG_CLK_INTL
[2:0])
- If Control registers changes, Some blocks will be reset automatically.
- In case, Auto reset does not work, these blocks’ reset can be done manually.
- MPEC IF Clock is made by Control Register and the Rules are as follows
- Tmp = (fMCLK/fSR)*(1/(2*CR)), fMCLK : System Clock Frequency,fSR : Symbol Rate, CR : Code
Rate
MCLK=88 MHz
MPEG Clock (MHz)
Control
Register
(0x22)
MPEG
Clock(Parallel)
MPEG Clock
(Serial)
Range
Divide
Serial
Parallel
0
1
2
3
4
5
6
7
F
MCLK
/8
F
MCLK
/16
F
MCLK
/32
F
MCLK
/64
F
MCLK
/96
F
MCLK
/128
F
MCLK
/192
F
MCLK
/256
F
MCLK
F
MCLK
/2
F
MCLK
/4
F
MCLK
/8
F
MCLK
/12
F
MCLK
/16
F
MCLK
/24
F
MCLK
/32
1
<
Tmp
≤
2
2
<
Tmp
≤
5
5
<
Tmp
≤
9
9
<
Tmp
≤
13
13
<
Tmp
≤
17
17
<
Tmp
≤
25
25
<
Tmp
≤
33
33
<
Tmp
1
2
3
4
5
6
7
8
88
44
22
11
11
5.5
2.75
1.375
0.9166625
0.6875
0.458325
0.34375
7.3333
5.5
3.6666
2.75
Example1) System Clock Frequency = 88MHZ, Symbol Rate : 44MSps
Code Rate
Tmp Value
1/2
2
2/3
1.5
3/4
1.333
5/6
1.2
6/7
1.166
7/8
1.142
Setting Control Register Value
1
0
0
0
0
0
Samsung Electronics Co, Ltd. Proprietary Information
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