參數(shù)資料
型號： S5H1420
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Channel Decoder for DVB-S/DSS
中文描述： 頻道解碼器DVB-S/DSS
文件頁數(shù)： 28/31頁
文件大?。?/td> 849K
代理商： S5H1420
S5H1420
DBS Channel Decoder for DVB-S/DSS
-28
5.6 I
2
C bus characteristics
Symbol
Parameter
Test Condition
s
Min
Typ
Max
Unit
V
IL
V
IH
Low Level input Voltage
High Level input Voltage
Pull up to 5V
10%
- 0.5
2.0
0.8
5.5
V
V
V
OH
V
OL
High Level output Voltage
Low Level output Voltage
Pull up to 5V
10%
5.5
0.4
V
V
I
LK
Input Leakage Current
VIN = 0V to 5V
-10
10
uA
C
IN
Input Capacitance
0
3.5
pF
I
OL
Output Sink Current
VOL = 0.5V
10
mA
f
SCLN
f
SCLS
SCL Clock Frequency
Normal Mode
Standby Mode
0
0
f
M_CLK
/40
f
M_CLK
/10
_
_
t
BUF
Bus Free Time between a STOP and START
Condition
1.3
us
t
HD,STA
Hold Time(repeated)START Condition. After
this period, the first clock pulse is generated
0.6
us
t
LOW
t
HIGH
Low Period of the SCL Clock
High Period of the SCL Clock
1.3
0.6
us
us
t
SU,STA
Setup Time for a repeated START Condition
0.6
us
t
SU,STO
Setup Time for STOP Condition
0.6
us
t
SU,DAT
Data Setup Time
100
ns
t
R
, t
F
Rise and Fall Time of both SDA and SCL
signals
300
ns
C
B
Capacitive Load for each Bus Line
400
pF
±
±
I
2
C bus timing diagram
Samsung Electronics Co, Ltd. Proprietary Information
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參數(shù)描述
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