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參數(shù)資料
| 型號(hào)： | S5935TFC |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI Product |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁(yè)數(shù)： | 61/204頁(yè) |
| 文件大?。?/td> | 1897K |
| 代理商： | S5935TFC |
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S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 61
OUTGOING MAILBOX REGISTERS (OMB)
Register Names
Outgoing Mailboxes 1-4
These four DWORD registers provide a method for sending command or
parameter data to the Add-On system. PCI bus operations to these regis-
ters may be in any width (byte, word, or DWORD). Writing to these regis-
ters can be a source for Add-On bus interrupts (if desired) by enabling
their interrupt generation through the use of the Add-On’s interrupt con-
trol/status register.
PCI Address Offset
00h, 04h, 08h, 0Ch
Power-up value
XXXXXXXXh
Attribute
Read/Write
Size
32 bits
INCOMING MAILBOX REGISTERS (IMB)
Register Names
Incoming Mailboxes 1-4
These four DWORD registers provide a method for receiving user defined
data from the Add-On system. PCI bus read operations to these registers
may be in any width (byte, word, or DWORD). Only read operations are
supported. Reading from these registers can optionally cause an Add-On
bus interrupt (if desired) by enabling their interrupt generation through the
use of the Add-On’s interrupt control/status register. Mailbox 4, byte 3 only
exists as device pins on the S5935 devices when used with a serial non-
volatile memory.
PCI Address Offset
10h, 14h, 18h, 1Ch
Power-up value
XXXXXXXXh
Attribute
Read Only
Size
32 bits
FIFO REGISTER PORT (FIFO)
Register Name
FIFO Port
This location provides access to the bidirectional FIFO. Separate registers
are used when reading from or writing to the FIFO. Accordingly, it is not
possible to read what was written to this location. The FIFO registers are
implicitly involved in all bus master operations and, as such, should not be
accessed during active bus master transfers. When operating upon the
FIFOs with software program transfers involving word or byte operations,
the endian sequence of the FIFO should be established as described
under FIFO Endian Conversion Management in order to preserve the
internal FIFO data ordering and flag management. The FIFO’s fullness
may be observed by reading the master control-status register or MCSR
register.
PCI Address Offset
20h
Power-up value
XXXXXXXXh
Attribute
Read/Write
Size
32 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935TF | PCI 5V Bus Master/Target Device 32-bit |
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TRW | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S5943 | 制造商:MERKLE-KORFF INDUSTRIES 功能描述:OLD COLMAN P/N: SD13537680 |
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