- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374668 > S5935TFC (APPLIEDMICRO INC) PCI Product PDF資料下載
參數(shù)資料
| 型號(hào)： | S5935TFC |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Product |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁(yè)數(shù)： | 151/204頁(yè) |
| 文件大?。?/td> | 1897K |
| 代理商： | S5935TFC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)當(dāng)前第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)
S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 151
Pass-Thru Status/Control Signals
The S5935 Pass-Thru registers are accessed using
the standard Add-On register access pins. The Pass-
Thru Address Register (APTA) can, optionally, be
accessed using a single, direct access input, PTADR#.
Pass-Thru cycle status indicators are provided to con-
trol Add-On logic based on the type of Pass-Thru
access occurring (single cycle, burst, etc.). The follow-
ing signals are provided for Pass-Thru operation:
Pass-Thru Add-On Data Bus Sizing
Many applications require an 8-bit or 16-bit Add-On
bus interface. Pass-Thru regions can be configured to
support bus widths other than 32-bits. Each Pass-Thru
region can be defined, during initialization, as 8, 16-,
or 32-bits. All of the regions do not need to be the
same. This feature allows a simple interface to 8-and
16-bit Add-On devices.
To support alternate Add-On bus widths, the S5935
performs internal data bus steering. This allows the
Add-On interface to assemble and disassemble 32-bit
PCI data using multiple Add-On accesses to the Pass-
Thru Data Register (APTD). The Add-On byte enable
inputs (BE[3:0]#) are used to access the individual
bytes or words within APTD.
BUS INTERFACE
The Pass-Thru interface on the S5935 is a PCI target-
only function. Pass-Thru operation allows PCI initia-
tors to read or write resources on the Add-On card. A
PCI initiator may access the Add-On with single data
phase cycles or multiple data phase bursts.
The Add-On interface implements Pass-Thru status
and control signals used by logic to complete data
transfers initiated by the PCI bus. The Pass-Thru inter-
face is designed to allow Add-On logic to function with-
out knowledge of PCI bus activity. Add-On logic only
needs to react to the Pass-Thru status outputs. The
S5935 PCI interface independently interacts with the
PCI initiator to control data flow between the devices.
The following sections describe the PCI and Add-On
bus interfaces. The PCI interface description provides
a basic overview of how the S5935 interacts with the
PCI bus, and may be useful in system debugging. The
Add-On interface description indicates functions
required by Add-On logic and details the Pass-Thru
handshaking protocol.
PCI Bus Interface
The S5935 decodes all PCI bus cycle addresses. If
the address associated with the current cycle is to one
of S5935 Pass-Thru regions, DEVSEL# is asserted. If
the Pass-Thru logic is currently idle (not busy finishing
a previous Pass-Thru operation), the bus cycle type is
decoded and the Add-On Pass-Thru status outputs
are set to initiate a transfer on the Add-On side. If the
Pass-Thru logic is currently busy completing a previ-
ous access, the S5935 signals a retry to PCI initiator.
The following sections describe the behavior of the
PCI interface for Pass-Thru accesses to the S5935.
Single cycle accesses, burst accesses, and target-ini-
tiated retries are detailed.
PCI Pass-Thru Single Cycle Accesses
Single cycle transfers are the simplest PCI bus trans-
action. Single cycle transfers have an address phase
and a single data phase. The PCI bus transaction
starts when an initiator drives address and command
information onto the PCI bus and asserts FRAME#.
The initiator always deasserts frame before the last
data phase. For single cycle transfers, FRAME# is
only asserted during the address phase (indicating the
first data phase is also the last).
When the S5935 sees FRAME# asserted, it samples
the address and command information to determine if
the bus transaction is intended for it. If the address is
within one of the defined Pass-Thru regions, the
S5935 accepts the transfer (assert DEVSEL#), and
Signal
Function
PTATN#
This output indicates a Pass-Thru access
is occurring
PTBURST#
This output indicates the Pass-Thru
access is a PCI burst access
PTNUM[1:0]
These outputs indicate which Pass-Thru
region decoded the PCI address
PTBE[3:0]#
These outputs indicate which data bytes
are valid (PCI writes), or requested (PCI
reads)
PTWR
This output indicates if the Pass-Thru
access is a PCI read or a write
PTADR#
When asserted, this input drives the
Pass-Thru Address Register contents
onto the Add-On data bus
PTRDY#
When asserted, this input indicates the
current Pass-Thru transfer has been com-
pleted by the Add-On
BPCLK
Buffered PCI bus clock output (to syn-
chronize Pass-Thru data register
accesses)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935TF | PCI 5V Bus Master/Target Device 32-bit |
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TRW | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S5943 | 制造商:MERKLE-KORFF INDUSTRIES 功能描述:OLD COLMAN P/N: SD13537680 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。