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參數(shù)資料
| 型號(hào)： | S5935TFC |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Product |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁(yè)數(shù)： | 154/204頁(yè) |
| 文件大?。?/td> | 1897K |
| 代理商： | S5935TFC |
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S5935 – PCI Product
154 DS1527
AMCC Confidential and Proprietary
Revision 1.02 – June 27, 2006
Data Book
Figure 2 shows a single cycle Pass-Thru write using
the Pass-Thru address information. This provides PCI
cycle address information to select a specific address
location within an Add-On memory or peripheral. Add-
On logic must latch the address for use during the data
transfer. Typically, the entire 32-bit address is not
required. The Add-On may implement a scheme
where only the required number of address bits are
latched. It may also be useful to use the Pass-Thru
region identifiers, PTNUM[1:0] as address lines. For
example, Pass-Thru region 1 might be a 64K block of
SRAM for data, while Pass-Thru region 2 might be
64K of SRAM for code storage (down-loaded from the
host during initialization). Using PTNUM0 as address
line A16 allows two unique Add-On memory regions to
be defined.
Figure 81. Single Cycle Pass-Thru Write with PTADR#
Clock 0:
The PCI bus cycle address information is stored in the S5935 Pass-Thru Address Register.
Clock 1:
The PCI address is recognized as a write to Pass-Thru region 1. The PCI data is stored in the S5935 Pass-Thru
Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring.
Clock 2:
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
PTBURST#
Deasserted. The access has a single data phase.
PTNUM[1:0]
01. Indicates the PCI access is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru access is a write.
PTBE[3:0]#
0h. Indicates the Pass-Thru access is 32-bits.
SELECT#, address and byte enable inputs are driven to read the Pass-Thru Data Register at offset 2Ch.
DQ[31:0] are driven after RD# and SELECT# are asserted.
Clock 3:
If PTRDY# is asserted at the rising edge of clock 3, PTATN# is immediately deasserted and the Pass-Thru
access is completed at clock 4.
Clock 4:
If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals),
PTRDY# can be delayed, extending the cycle. With PTRDY# asserted at the rising edge of clock 4, PTATN# is
deasserted and the Pass-Thru access is completed at clock 5.
Clock 5:
PTATN# and PTBURST# deasserted at the rising edge of clock 5 indicates the Pass-Thru access is complete.
The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 6.
BPCLK
012345
6
0h
1
2Ch
0h
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
DQ[31:0]
PTRDY#
PTADR#
PT ADDR
PT DATA
PCI Write cycle completed
相關(guān)PDF資料 |
PDF描述 |
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| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
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