參數(shù)資料
型號(hào): S5935QRC
廠商: APPLIEDMICRO INC
元件分類(lèi): 總線控制器
英文描述: PCI Product
中文描述: PCI BUS CONTROLLER, PQFP160
封裝: GREEN, PLASTIC, QFP-160
文件頁(yè)數(shù): 25/204頁(yè)
文件大?。?/td> 1897K
代理商: S5935QRC
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S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 25
System Pins — PCI Local Bus
Signal
Type
Description
CLK
in
Clock. The rising edge of this signal is the reference upon which all other signals are based, with the
exception of RST# and the interrupt (IRQA#-). The maximum frequency for this signal is 33 MHz and the
minimum is DC (0 Hz).
RST#
in
Reset. This signal is used to bring all other signals within this device to a known, consistent state. All PCI
bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated.
Interface Control Pins — PCI Bus Signal
Signal
Type
Description
FRAME#
s/t/s
Frame. This signal is driven by the current bus master and identifies both the beginning and duration of
a bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and
that valid addresses and a corresponding bus command are present on the AD[31:00] and C/BE[3:0]
lines. FRAME# remains asserted during the data transfer portion of a bus operation and is deasserted
to signify the final data phase.
IRDY#
s/t/s
Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to
complete the current data phase of a bus transaction. For write operations, it indicates that valid data is
on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together.
TRDY#
s/t/s
Target Ready. This signal is sourced by the selected target and indicates that the target is able to com-
plete the current data phase of a bus transaction. For read operations, it indicates that the target is pro-
viding valid data on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted
together.
STOP#
s/t/s
Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop
the current transaction.
LOCK#
in
Lock. The lock signal provides for the exclusive use of a resource. The S5935 may be locked as a tar-
get by one master at a time. The S5935 cannot lock a target when it is a master.
IDSEL
in
Initialization Device Select. This pin is used as a chip select during configuration read or write opera-
tions.
DEVSEL#
s/t/s
Device Select. This signal is sourced by an active target upon decoding that its address and bus com-
mands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle.
Arbitration Pins (Bus Masters Only) — PCI Local Bus
Signal
Type
Description
REQ#
out
Request. This signal is sourced by an agent wishing to become the bus master. It is a point-to-point signal
and each master has its own REQ#.
GNT#
in
Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential bus master and sig-
nifies that access to the bus has been granted.
Error Reporting Pins — PCI Local Bus
Signal
Type
Description
PERR#
s/t/s
Parity Error. This pin is used for reporting parity errors during the data portion of a bus transaction for all
cycles except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks fol-
lowing the detection of the error. This signal is driven inactive (high) for one clock cycle prior to returning to
the tri-state condition.
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