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參數(shù)資料
| 型號： | S5935QRC |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Product |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | GREEN, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 149/204頁 |
| 文件大?。?/td> | 1897K |
| 代理商： | S5935QRC |
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S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 149
5. Define PCI to Add-On and Add-On to PCI FIFO
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
This must be programmed through the PCI
interface.
6. Define
These registers are written with the first address
that is to be accessed by the S5935. These
address registers are updated after each access
to indicate the next address to be accessed.
Transfers must start on DWORD boundaries.
MWARAllBus master write address
MRARAllBus master read address
7. Define transfer byte counts. These registers are
written with the number of bytes to be transferred.
The transfer count does not have to be a multiple
of four bytes. These registers are updated after
each transfer to reflect the number of bytes
remaining to be transferred. If transfer counts are
disabled, these registers do not need to be
programmed.
transfer
source/destination
address.
8. Enable Bus Mastering. Once steps 1-7 are com-
pleted, the FIFO may operate as a PCI bus
master. Read and write bus master operation
may be independently enabled or disabled. The
AMREN and AMWEN inputs control bus master
enabling for Add-On initiated bus mastering. The
MCSR bus master enable bits are ignored for
Add-On initiated bus mastering.
It is recommended that bus mastering be enabled as
the last step. Some applications may choose to leave
bus mastering enabled (AMREN and AMWEN
asserted) and start transfers by writing a non-zero
value to the transfer count registers (if they are
enabled).
If interrupts are enabled, an Add-On CPU interrupt
service routine is also required. The service routine
determines the source of the interrupt and resets the
interrupt. As mailbox registers may also be configured
to generate interrupts, the exact source of the interrupt
is indicated in the Add-On Interrupt Control Register
(AINT). Typically, the interrupt service routine is used
to setup the next transfer by writing new addresses
and transfer counts (if enabled), but some applications
may also require other actions. If read transfer or write
transfer complete interrupts are enabled, the master/
target abort interrupt is automatically enabled. These
indicate a transfer error has occurred. Writing a one to
these bits clears the corresponding interrupt.
PASS-THRU OVERVIEW
The S5935 provides a simple registered access port to
the PCI bus. Using a handshaking protocol with Add-
On card logic, the PCI bus directly accesses resources
on the Add-On. The Pass-Thru data transfer method is
very useful for direct Add-On memory access, or
accessing registers within peripherals on an Add-On
board. Pass-Thru operation requires an external nv
memory boot device to define and configure the
S5935 Pass-Thru regions.
The S5935 provides four user-configurable Pass-Thru
regions. Each region corresponds to a PCI Configura-
tion Base Address Register (BADR1-4). A region
represents a block of address space (the block size is
user-defined). Each block can be mapped into mem-
ory or I/O space. Memory mapped regions can request
to be located below 1 MByte (Real Mode address
space for a PC). Each region also has a configurable
bus width for the Add-On bus interface. An 8-, 16-, or
32-bit Add-On interface may be selected, for use with
a variety of Add-On memory or peripheral devices.
Pass-Thru features can be used only when the S5935
is a PCI target. As a target, the S5935 Pass-Thru
mode supports single data transfers as well as burst
transfers. When accessed with burst transfers, the
S5935 supports data transfers at the full PCI band-
width. The data transfer rate is only limited by the PCI
initiator performing the access and the speed of the
Add-On logic.
FUNCTIONAL DESCRIPTION
To provide the PCI bus Add-On with direct access to
Add-On resources, the S5935 has an internal Pass-
MCSR
Bit 12
Read vs. write priority
MCSR
Bit 8
Write vs. read priority
MWTC
All
Write transfer byte count
MRTC
All
Read transfer byte count
AINT
Bit 21
Master/target abort caused interrupt
AINT
Bit 19
Read transfer complete caused interrupt
AINT
Bit 18
Write transfer complete caused interrupt
相關PDF資料 |
PDF描述 |
|---|---|
| S5935TFC | PCI Product |
| S5935TF | PCI 5V Bus Master/Target Device 32-bit |
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
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