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參數(shù)資料
| 型號(hào)： | S5935QRC |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI Product |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | GREEN, PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 165/204頁(yè) |
| 文件大?。?/td> | 1897K |
| 代理商： | S5935QRC |
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S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 165
Add-On Pass-Thru Disconnect Operation
Slow PCI targets are prevented from degrading PCI
bus performance. The PCI specification allows only 16
clocks for a target to respond before it must request a
retry on single data phase accesses. For burst
accesses, the first data phase is allowed 16 clocks to
complete, all subsequent data phases are allowed 8
clocks each. This requirement allows other PCI initia-
tors to use the bus while the target requesting the retry
completes the original access.
Figure 8 shows the conditions that cause the S5935 to
request a retry from a PCI initiator on the first data
phase of a PCI read operation. FRAME# is asserted
during the rising edge of PCI clock 1. From this point,
the S5935 has 16 clock cycles to respond to the initia-
tor with TRDY# (completing the cycle). FRAME# could
remain asserted, indicating a burst read, but the retry
request conditions are identical for a single data phase
read and the first data phase of a burst read. BPCLK is
identical to PCICLK, lagging by a propagation delay of
a few nanoseconds (see Chapter 13). PTATN# is
asserted on the Add-On interface as soon as FRAME#
is sampled active at a PCICLK rising edge.
Figure 87. Target Requested Retry on the First PCI Data Phase
After PTATN# is asserted, PTRDY# must be asserted
by the 15th BPCLK rising edge to prevent the S5935
from requesting a retry. TRDY# is asserted on the PCI
interface one clock cycle after PTRDY# is asserted on
the Add-On interface. If Add-On logic does not return
PTRDY# by the 15th BPCLK rising edge, the S5935
asserts STOP#, requesting a retry from the PCI
initiator.
For Pass-Thru write operations, the S5935 never dis-
connects on the first or second PCI data phases of a
burst. The first data and second phases are always
accepted immediately by the S5935. No further action
is required by the PCI initiator. The only situation
where the S5935 may respond to a Pass-Thru write
with a retry request is after the second data phase of a
Pass-Thru burst write.
Figure 9 shows the conditions required for the S5935
to request a retry after the second data phase of a
burst transfer. This figure applies to both Pass-Thru
burst read and write operations.
18
17
16
15
4
3
2
1
17
16
15
14
3
2
1
PCICLK
FRAME#
STOP#
BPCLK
PTATN#
PTRDY#
PTRDY# must be asserted by
this time to present disconnecting
PTRDY# asserted too late so
S593X disconnects (asserts STOP#)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935TFC | PCI Product |
| S5935TF | PCI 5V Bus Master/Target Device 32-bit |
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935TF | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
| S5935TFC | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱(chēng):Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱(chēng):Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱(chēng):Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
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