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參數(shù)資料
| 型號： | S4405 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PECL的時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝時鐘發(fā)生器） |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 120K |
| 代理商： | S4405 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 7
AC SPECIFICATIONS
S4405
Table 4. AC Specifications
Symbol
Description
Min
Max
Min
Max
Units
f
VCO
VCO Frequency
160
266
160
320
MHz
f
REF
REFCLK Frequency
10
66
10
80
MHz
MPW
REF
REFCLK Minimum Pulse Width
5.0
5.0
ns
t
PE
Phase Error between TTLREF and FBCLK
-1
0
-1
0
ns
t
PEP
Phase Error between PECLREF and FBCLK
-3
-1
-3
-1
ns
t
PED
Phase Error Difference from Part to Part
1
0
750
0
750
ps
t
SKEW
Output Skew
2
(TTL)
0
400
0
400
ps
t
DC
Output Duty Cycle
45
55
45
55
%
f
PECL
PECLP/N Frequency
80
132
80
160
MHz
f
FOUT
FOUT Frequency
3
(TTL)
HFOUT Frequency
3
20
66
20
80
MHz
f
HFOUT
10
33
10
40
MHz
f
2XFOUT
2XFOUT Frequency
3
40
66
40
80
MHz
t
PS
Nominal Phase Shift Increment
3.75
6.25
3.125
6.25
ns
t
OFD
Tpd OUTEN0–2 to FOUTs, Disable
2
7
2
7
ns
t
OFE
Tpd OUTEN0–2 to FOUTs, Enable
2
7
2
7
ns
t
IRF
Input Rise/Fall Time
1
3
1
3
ns
t
ORF
FOUT Rise/Fall Time
4
0.5
1.5
0.5
1.5
ns
t
LOCK
Loop Acquisition Time
5
5
5
ms
S4405B-66
S4405B-80
1. Difference in phase error between two parts at the same voltage, temperature and frequency.
2. Output skew guaranteed for equal loading at each output.
3. C
= 35 pF.
4. With 35 pF output loading (0.8 V to 2.0 V transition).
5. Depends on loop filter chosen. (Number given is for example filter.)
Figure 5. Timing Waveforms
TTLREF, PECLREF
REF
MPW
FBCLK
FOUT0–3
OUTEN0–2
t
PE
REF
MPW
HFOUT, X2FOUT
t
SKEW
t
SKEW
t
OFD
t
OFE
Output Valid
Disabled
HFOUT, X2FOUT
FOUT0–3
PECLP
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