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參數(shù)資料
| 型號： | S4405 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PECL的時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝時鐘發(fā)生器） |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | S4405 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 2
S4405
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
This BiCMOS clock generator is designed to allow
the user to generate TTL clocks, in the 10–80 MHz
range, with less than 400 ps of skew. Implemented
in AMCC’s 1.0
μ
BiCMOS technology, the internal
VCO, phase detector, and programmable divider and
phase selector allow the user to tailor the TTL output
clocks for his/her system needs. The internal VCO
can operate between 160 to 320 MHz, and the pro-
grammability allows the user to generate TTL output
clocks in the 10–80 MHz range, and a differential
+5V referenced ECL output at 80–160 MHz.
The clock generator offers the user the ability to se-
lect the appropriate phase relationship among the
four FOUT0–3 TTL clock outputs. The phase selec-
tion choices are shown in Table 2.
The clock generator also allows the user to choose
the divide-by ratio between the VCO frequency and
the frequency of the FOUT0–3 signals. The VCO fre-
quency can be divided by 4 when DIVSEL is low, and
divided by 8 when DIVSEL is high. The divide ratio
between the VCO and the pseudo ECL outputs,
PECLP and PECLN, is a fixed divide-by-2.
The clock generator also has two output enable in-
puts which can be used to control which outputs
toggle. OUTEN0 controls the HFOUT and X2FOUT
outputs, and OUTEN1 controls the FOUT0–3 out-
puts. When the output enables are high, the outputs
are disabled, and held in a high state.
REFCLK can be driven by either the TTLREF or
PECLREF inputs. The reference clock source is se-
lected with the INPSEL input. When INPSEL is low,
the TTLREF input is selected as the reference clock.
The FOUT0–3 outputs are the main TTL output
clocks that the generator supplies. The frequency of
these outputs is determined by the REFCLK clock
frequency and the output clock that is tied to the
FBCLK input. FOUT0–3 will be equal to REFCLK,
half of REFCLK, or twice the frequency of REFCLK.
The X2FOUT TTL output provides a clock signal that
is identical to the FOUT0 output in the divide-by-4
mode, but twice the FOUT0 frequency (max. freq. of
66 MHz) in the divide-by-8 mode. The HFOUT TTL
output provides a clock signal that is also in phase with
the FOUT0 output, but at half the FOUT0 frequency.
FILTER is the analog signal from the phase detector
going into the VCO. This pin is provided so a simple
external filter (a single resistor and one capacitor)
can be included in the phase-locked loop of the clock
generator.
The LOCK output goes high when the reference
clock and FBCLK are within 2–4 ns of each other.
This output tells the user that the PLL is in lock.
Three pins are included for test purposes. TESTEN
allows the chip to use the REFCLK signal instead of
the VCO output to clock the chip. This is used during
chip test to allow the counters and control logic to be
tested independently of the VCO. The RESET pin
initializes the internal counter flip-flops to zeros, but
several clock cycles are necessary before the out-
puts go to a zero state.
The minimum phase delay between FOUT0–3 sig-
nals is a function of the VCO frequency. The VCO
frequency can be determined by multiplying the out-
put frequency by the divide-by ratio of four or eight.
The minimum phase delay is equal to the period of
the VCO frequency: M
= 1/VCO freq. Since the VCO
can operate in the 160 MHz to 320 MHz range, the
range of minimum phase delay values is 6.25 ns to
3.125 ns. Table 1 shows various FOUT/VCO fre-
quencies and the associated phase resolution.
The charge pump and VCO portion of the chip use a
separate analog power supply. This supply is brought
onto the chip through a distinct set of power and
ground pins. This supply should be free of digital
switching noise.
Example:
In a typical system, designers may need several low-
skew outputs, one early clock, one late clock, a clock
at half the input clock frequency, and one at twice
the input clock frequency. This system requirement
FOUT0–3
Freq
Divider
Select
VCO
Freq
Min Phase
Resolution
80 MHz
66 MHz
50 MHz
40 MHz
40 MHz
33 MHz
25 MHz
20 MHz
4
4
4
4
8
8
8
8
320 MHz
266 MHz
200 MHz
160 MHz
320 MHz
266 MHz
200 MHz
160 MHz
3.125 ns
3.75 ns
5.0 ns
6.25 ns
3.125 ns
3.75 ns
5.0 ns
6.25 ns
Table 1. Example Phase Resolution
PHSEL1
0
0
PHSEL0
0
1
Phase Relationship
All at same phase
Outputs skewed by 90 degrees from
each other
FOUT1 leads FOUT0 by minimum
phase, FOUT2 lags FOUT0 by
minimum phase, and FOUT3 lags
FOUT0 by 90 degrees
Outputs skewed by minimum phase
(determined by the divider selection,
and the VCO frequency) from each
other.
1
0
1
1
Note:
The PECL output is not affected by the phase select inputs.
Table 2. Phase Selections
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