
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 5
Table 3. Output Select Matrix
Configuration
Number
Select Pins
Output Fed
to FBCLK
Output Phase Relationships
÷
4
X2FOUT
÷
8
PHSEL1 PHSEL0
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
FOUT0–FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (
÷
8)
0
0
0
0
0/2
0
0/4
0/2
–Q/2
–2Q/2
–3Q/2
0
0/4
0/2
t/2
–t/2
–Q/2
0
0/4
0/2
–t/2
–2t/2
–3t/2
0
0/4
0
2(0)
4(0)
0
2(0)
2(–Q)
2(–2Q)
2(–3Q)
4(0)
0
2(0)
2(t)
2(–t)
2(–Q)
4(0)
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
2(0)
0/2
0
–Q
–2Q
–3Q
2(0)
0/2
0
t
–t
–Q
2(0)
0/2
0
–t
–2t
–3t
2(0)
0/2
2(0)
0/2
Q
0
–Q
–2Q
2(Q)
Q/2
–t
0
–2t
–Q–t
2(–t)
–t/2
t
0
–t
–2t
2(t)
t/2
2(0)
0/2
2Q
Q
0
–Q
2(2Q)
2Q/2
t
2t
0
–Q+t
2(t)
t/2
2t
t
0
–t
2(2t)
2t/2
2(0)
0/2
3Q
2Q
Q
0
2(3Q)
3Q/2
Q
Q+t
Q–t
0
2(Q)
Q/2
3t
2t
t
0
2(3t)
3t/2
2(0)
0
–Q
–2Q
–3Q
2(0)
0
t
–t
–Q
2(0)
0
–t
–2t
–3t
2(0)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
“0” implies the output is aligned with the reference clock.
“t” implies the output lags the reference clock by a minimum phase delay.
“Q” implies the output lags the reference clock by 90
°
of phase.
“–t” implies the output leads the reference clock by a minimum phase delay.
“–Q” implies the output leads the reference clock by 90
°
of phase.
“2( )” implies the output is at twice the frequency of the reference clock.
“/2” implies the output is at half the frequency of the reference clock.
The PECLN/P Differential PECL output is not affected by the PHSEL inputs.
0
t
–t
2t
TTLREF
0
Q
2Q
–Q
TTLREF
2(0)
0/2
0/4
4(0)
TTLREF
0° 90°180°
Table
entry
Table
entry
Table
entry
Waveform
Waveform
Waveform
–t
t 2t
–90°
Legend
OUTPUT SELECT MATRIX
S4405