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參數(shù)資料
| 型號： | S4405 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PECL的時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝時鐘發(fā)生器） |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | S4405 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 4
The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
The analog VCC plane should be separated from the
digital VCC and ground planes by at least 1/8 inch.
S4405
PIN DESCRIPTIONS
PHSEL0.
This input, along with PHSEL1, allows se-
lection of the phase relationship among the four
FOUT0–FOUT3 outputs. See Tables 2 and 3 for the
selection choices.
PHSEL1.
Along with PHSEL0, allows selection of the
phase relationship among the four FOUT0–FOUT3
outputs. See Tables 2 and 3 for the selection
choices.
OUTEN0.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the frequency
doubler output (X2FOUT) and the half-frequency out-
put (HFOUT).
OUTEN1.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the FOUT0–
FOUT3 outputs.
RESET.
Active Low. Initializes internal states for test
purposes.
TSTEN.
Active High. Allows REFCLK to drive the
divider phase adjust circuitry, after the first divide-by-
two stage. Therefore, REFCLK can be divided by two
in the divide-by-four mode, and divided by four in the
divide-by-eight mode, and used to directly sequence
the outputs.
INPSEL.
Allows user to select between TTLREF and
PECLREF reference frequencies. When INPSEL is
High, the PECLREF input is selected.
Output Signals
FILTER.
A tap between the analog output of the
phase detector and the VCO input. Allows a simple
external filter (a single resistor and capacitor) to be
included in the PLL.
X2FOUT.
Provides a clock signal identical to the
FOUT0 output in the divide-by-four mode and twice
the FOUT0 frequency (maximum of 80 MHz) in the
divide-by-eight mode.
FOUT0.
Clock output.
FOUT1.
Clock output.
FOUT2.
Clock output.
FOUT3.
Clock output.
HFOUT.
Provides a clock signal in phase with the
FOUT0 output, but at half the FOUT0 frequency in
both the divide-by-four and divide-by-eight modes.
PECLP/N.
Differential PECL output, always one-half
the VCO frequency.
LOCK.
Goes high when the reference clock and
FBCLK are within 2–4 ns of each other, demonstrat-
ing that the PLL is in lock.
Test Capabilities
The TSTEN input allows users to bypass the VCO and
provide their own clock through the selected reference
clock input. When TSTEN is High, the VCO is turned
off and the REFCLK signal drives the divider/phase
adjust circuitry, directly sequencing the outputs. The
TSTEN and REFCLK inputs join the divider circuitry
after the initial divide-by-two stage. Therefore, REFCLK
is divided by two in the divide-by-four mode and di-
vided by four in the divide-by-eight mode.
PIN DESCRIPTIONS
Input Signals
TTLREF.
TTL. Frequency reference supplied by the
user that, along with the output tied to the FBCLK
input, determines the frequency of the FOUT0–
FOUT3 outputs. INPSEL is used to select between
this reference and the PECL reference PECLREFP/N.
PECLREFP/N.
Differential PECL. Frequency refer-
ence supplied by the user. Selectable by the INPSEL
input.
FBCLK.
Feedback clock that, along with the refer-
ence clock input, determines the frequency of the
FOUT0–FOUT3 outputs. One output is selected to
feed back to this input. (See Table 3.)
DIVSEL.
Controls the divider circuit that follows the
VCO. When DIVSEL is low, the VCO frequency is
divided by four. When DIVSEL is high, the VCO fre-
quency is divided by eight. (See Tables 1 and 3.)
34
33
32
31
1.5K
0.1
μ
F
0.1
μ
F
A +5V
D GND
D +5V
FB2
FB1
S4405
A GND
Figure 4. Board Layout
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