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參數(shù)資料
| 型號： | S4405 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PECL的時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝時鐘發(fā)生器） |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 120K |
| 代理商： | S4405 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 1
DEVICE SPECIFICATION
BiCMOS PECL CLOCK GENERATOR
S4405
FEATURES
Generates six clock outputs from 20 MHz to 80
MHz (HFOUT operates from 10 MHz to 40 MHz)
Allows PECL or TTL reference input
Provides differential PECL output at up to 160
MHz
21 selectable phase/frequency relationships for
the clock outputs
Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
TTL outputs have less than 400 ps maximum
skew
Lock Detect output indicates loop status
Internal PLL with VCO operating at 160 to 320
MHz
Test Enable input allows VCO bypass for open-
loop operation
Maximum 1.0 ns of phase error (750 ps from
part to part)
Proven 1.0 micron BiCMOS technology
Single +5V power supply operation
44 PLCC package
APPLICATIONS
CMOS ASIC Systems
High-speed Microprocessor Systems
Backplane Clock Deskew and Distribution
GENERAL DESCRIPTION
The S4405 BiCMOS clock generators allow the user
to generate multiphase TTL clocks in the 10–80 MHz
range with less than 400 ps of skew. Use of a simple
off-chip filter allows an entire 160–320 MHz phase-
locked loop (PLL) to be implemented on-chip. Divide-
by-two and times-two outputs allow the ability to
generate output clocks at half, equal to, or twice the
reference clock input frequency. The reference is se-
lectable to be either TTL or PECL. By using the pro-
grammable divider and phase selector, the user can
select from up to 21 different output relationships.
The outputs can be phase-adjusted in increments as
small as 3.125 ns to tailor the clocks to exact system
requirements.
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4405 generates six TTL outputs
and one differential PECL output. Output enables are
provided for the various TTL banks, allowing clock
control for board and system tests.
Figure 1. Clock Generator Block Diagram
PHASE
DETECTOR
CHARGE
PUMP
VCO
I
0
I
1
MUX
SELECT
TTLREF
REFCLK
FBCLK
TSTEN
DIVSEL
PHSEL0
PHSEL1
RESET
OUTEN0
OUTEN1
DIVIDER
AND
PHASE
CONTROL
LOGIC
HFOUT
X2FOUT
FOUT0
FOUT1
FOUT2
FOUT3
LOCK
FILTER
Digital
+5V
0V
14K
Analog
+5V
0V
÷ 2
PECLP
PECLN
MUX
PECLREFP
INPSEL
I
0
I
1
S
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