- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374667 > S4405 (Applied Micro Circuits Corp.) BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) PDF資料下載
參數(shù)資料
| 型號： | S4405 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PECL Clock Generator(能產(chǎn)生6個時鐘輸出的BiCMOS時鐘發(fā)生器) |
| 中文描述： | BiCMOS工藝PECL的時鐘發(fā)生器（能產(chǎn)生6個時鐘輸出的BiCMOS工藝時鐘發(fā)生器） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | S4405 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 3
FUNCTIONAL DESCRIPTION
S4405
can be met by setting PHSEL1 to 1, PHSEL0 to 0,
and feeding back FOUT0 to the FBCLK input (Row
10 of Table 3). The result is that FOUT0 will be
phase-aligned to the reference clock, FOUT1 will
lead the reference clock by a minimum phase delay,
FOUT2 will lag the reference clock by a minimum
phase delay, FOUT3 will phase-lag the reference
clock by 90
°
, HFOUT will be phase-aligned with the
reference clock but at half the frequency, and
X2FOUT will be either phase-aligned at the same
frequency as the reference clock if DIVSEL = 0, or at
twice the frequency if DIVSEL = 1.
Enabling Outputs
The S4405 has two output-enable inputs that control
which outputs toggle. When held LOW, OUTEN0
controls the frequency doubler output X2FOUT and
the half-frequency output HFOUT. OUTEN1 controls
the FOUT0–3 outputs. When an output enable pin is
held High, its associated outputs are disabled and
held in a High state.
Filter
The FILTER output is a tap between the analog out-
put of the phase detector and the VCO input. This pin
allows a simple external filter (Figure 2) to be in-
cluded in the PLL. AMCC recommends the use of the
filter component values shown. This filter was chosen
for its ability to reduce the output jitter and filter out
noise on the reference clock input.
Reset
When the RESET pin is pulled low, all the internal
states go to zero, but the outputs will not go low until
one clock cycle later (VCO/2 or period of the refer-
ence clock). After the chip is reset, the PLL requires
a resynchronization time before lock is again achieved.
Lock Detect
A lock detect function is provided by the LOCK out-
put. When the selected reference clock and FBCLK
Figure 2. External PLL Filter
Figure 3. External Power Supply Filter
ANALOG +5V
0.1 μF
DIGITAL +5V
DIGITAL GND
ANALOG GND
FB1
FB2
10 μF
Tantalum
(optional)
are within 2–4 ns of each other, the PLL is in lock,
and the LOCK output goes High.
Power Supply Considerations
Power for the analog portion of the S4405 chips must
be isolated from the digital power supplies to mini-
mize noise on the analog power supply pins. This
isolation between the analog and digital power sup-
plies can be accomplished with a simple external
power supply filter (Figure 3). The analog power
planes are connected to the digital power planes
through single ferrite beads (FB1 and FB2) or induc-
tors capable of handling 25 mA. The recommended
value for the inductors is in the range from 5 to
100
μ
H, and depends upon the frequency spectrum of
the digital power supply noise. The ferrite beads
should exhibit 75
impedance at 10 MHz.
Decoupling capacitors are also very important to
minimize noise. The decoupling capacitors must
have low lead inductance to be effective, so ceramic
chip capacitors are recommended. Decoupling ca-
pacitors should be located as close to the power pins
as physically possible. And the decoupling should be
placed on the top surface of the board between the
part and its connections to the power and ground
planes.
BOARD LAYOUT CONSIDERATIONS
The S4405 is sensitive to noise on the Analog +5 V
and Filter pins. Care should be taken during board
layout for optimum results.
All decoupling capacitors (C1–C4 = 0.1
μ
F) should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4405 and the power and ground plane connections.
No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 4) to avoid the possibility of noise due
to crosstalk.
A +5V
0.1 μF
1.5k
32
31
S4405
A VCC
FILTER
相關PDF資料 |
PDF描述 |
|---|---|
| S4406 | 12-Output BiCMOS PLL Clock Generator(能產(chǎn)生12個時鐘輸出的BiCMOS鎖相環(huán)時鐘發(fā)生器) |
| S4503 | BiCMOS Clock Synthesizer(帶可編程時鐘輸出的BiCMOS時鐘合成器) |
| S4505 | RAMBUS COMPATIBLE CLOCK GENERATORS |
| S4505S | RAMBUS COMPATIBLE CLOCK GENERATORS |
| S4506 | RAMBUS COMPATIBLE CLOCK GENERATORS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S-4406-AB | 制造商:Molex 功能描述: |
| S-4406-DB | 制造商:Molex 功能描述: |
| S-4406-SB | 制造商:Molex 功能描述: |
| S4-40-7/16-2701 | 制造商:APM HEXSEAL 功能描述:SEELSCREW TYPE S |
| S-4408-AB | 制造商:Molex 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。