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參數(shù)資料
| 型號(hào)： | S3C70F4XX-AV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 |
| 封裝： | 0.400 INCH, SDIP-30 |
| 文件頁數(shù)： | 174/179頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S3C70F4XX-AV |
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S3C70F2/C70F4/P70F4
INTERRUPTS
7-7
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. The IPR is mapped to
RAM address FB2H, and its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions,
all interrupts must first be disabled by a DI instruction.
FB2H
IME
IPR.2
IPR.1
IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or
you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by
a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by
any other interrupt source.
Interrupt
Default Priority
INTB
1
INT0
2
INT1
3
INTS
4
INTT0
5
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if
an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the
IME flag is set to logic one.
The IME flag is mapped to FB2H.3 and can be directly manipulated by EI and DI instructions, regardless of the
current enable memory bank (EMB) value.
Table 7-4. Interrupt Priority Register Settings
IPR.2
IPR.1
IPR.0
Result of IPR Bit Setting
0
Normal interrupt handling according to default priority settings
0
1
Process INTB interrupt at highest priority.
0
1
0
Process INT0 interrupts at highest priority.
0
1
Process INT1 interrupts at highest priority.
1
0
Process INTS interrupts at highest priority.
1
0
1
Process INTT0 interrupts at highest priority.
NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt generated
first will become high priority. Therefore, the first generated interrupt cannot be superceded by any other interrupt. If
two or more interrupt requests are received simultaneously, the priority level is determined according to the
standard interrupt priorities in Table 7.4 (e.g., the default priority assigned by hardware when the lower three IPR
bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then,
when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited interrupt
service routine is started.
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