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參數(shù)資料
| 型號： | S3C70F4XX-AV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 |
| 封裝： | 0.400 INCH, SDIP-30 |
| 文件頁數(shù)： | 101/179頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S3C70F4XX-AV |
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S3C70F2/C70F4/P70F4
ADDRESS SPACES
2-15
PUSH OPERATIONS
Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the
stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number
determined by the type of push operation and then points to the next available stack location.
PUSH Instructions
A PUSH instruction refers the SP to write two 4-bit data nibbles from the PC to the stack. Two 4-bit stack
addresses are referred by the stack pointer: one for the upper register value and another for the lower register.
After the PUSH has executed, the SP is decremented by two and points to the next available stack location.
CALL Instructions
When a subroutine call is issued, the CALL instruction refers the SP to write the PC's contents to six 4-bit stack
locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are
also pushed to the stack. After the CALL has executed, the SP is decremented by six and points to the next
available stack location. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to
the number of levels permitted in the stack.
Interrupt Routines
An interrupt routine refers the SP to push the contents of the PC, as well as current values for the program status
word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed,
the SP is decremented by six and points to the next available stack location. During an interrupt sequence,
subroutines may be nested up to the number of levels which are permitted in the stack area.
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
SP - 2
SP - 1
SP
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
CALL
(After CALL, SP
SP - 6)
EMB
ERB
0
PC3 - PC0
PC7 - PC4
0
PUSH
(After PUSH, SP
SP - 2)
LOWER REGISTER
UPPER REGISTER
(When INT is acknowledged,
SP
SP - 6)
INTERRUPT
0
PC3 - PC0
PC7 - PC4
IS1
IS0
EMB
ERB
PSW
C
SC2
SC1
SC0
0
PC 11-PC 8
Figure 2-7. Push-Type Stack Operations
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