- 您現(xiàn)在的位置：買賣IC網 > PDF目錄98069 > S3C70F4XX-AV 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 PDF資料下載
參數(shù)資料
| 型號： | S3C70F4XX-AV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 |
| 封裝： | 0.400 INCH, SDIP-30 |
| 文件頁數(shù)： | 106/179頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S3C70F4XX-AV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁當前第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁
S3C70F2/C70F4/P70F4
ADDRESS SPACES
2-19
INTERRUPT STATUS FLAGS (IS0, IS1)
PSW bits IS0 and IS1 contain the current interrupt execution status values. They are mapped to RAM bit loca-
tions FB0H.2 and FB0H.3, respectively. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control
instructions
By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process
multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit
determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status
flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined
by the IPR.
When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically
incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruc-
tion, IS0 and IS1 values are restored to the PSW. Table 2–6 shows the effects of IS0 and IS1 flag settings.
Table 2-6. Interrupt Status Flag Bit Settings
IS1
Value
IS0
Value
Status of Currently
Executing Process
Effect of IS0 and IS1 Settings
on Interrupt Request Control
0
All interrupt requests are serviced
0
1
Only high-priority interrupt(s) as determined in the
interrupt priority register (IPR) are serviced
1
0
2
No more interrupt requests are serviced
1
—
Not applicable; these bit settings are undefined
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-
rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-
struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI in-
struction to re-enable interrupt processing.
+
+PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:
INTB
DI
; Disable interrupt
BITR
IS1
; IS1
← 0
BITS
IS0
; Allow interrupts according to IPR priority level
EI
; Enable interrupt
相關PDF資料 |
PDF描述 |
|---|---|
| S3C72M9XX-QA | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3P72M9-QA | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3C7414XX-AQ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42 |
| S3C7414XX-QZ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| S3P7414XX-QZ | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP44 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S3C7235 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7238 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7281 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM, RAM. |
| S3C7295 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M |
| S3C72B5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A |
發(fā)布緊急采購，3分鐘左右您將得到回復。