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參數(shù)資料
| 型號： | S3C70F2XX-SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
| 封裝： | 0.450 INCH, SOP-32 |
| 文件頁數(shù)： | 5/179頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S3C70F2XX-SO |
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S3C70F2/C70F4/P70F4
POWER-DOWN
8-1
8
POWER-DOWN
OVERVIEW
The S3C70F2/C70F4 microcontroller has two power-down modes to reduce power consumption: idle and stop.
Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions
must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while pe-
ripherals and the oscillation source continue to operate normally.
When
RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and
the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
In stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware
components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU,
basic timer, serial I/O, timer/ counters 0, and watch timer — and on external interrupt requests, is detailed in
Table 8-1.
NOTE
Do not use stop mode if you are using an external clock source because Xin input must be restricted
internally to VSS to reduce current leakage.
Idle or stop modes are terminated either by a
RESET, or by an interrupt with the exception of INT0, which are
enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by
RESET input,
a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag
are set to "1", power-down mode is released immediately upon entering power-down mode.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the
interrupt master enable flag (IME):
— If the IME flag = "0", program execution is started immediately after the instruction which issues the request
to enter power-down mode. The interrupt request flag remains set to logic one.
— If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored
interrupt is initiated. However, when the release signal is caused by INTK or INTW, the operation is identical
to the IME = 0 condition. That is, a vector interrupt is not generated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3C70F4 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7235 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7238 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7281 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM, RAM. |
| S3C7295 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M |
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