參數(shù)資料
型號(hào): S3C70F2XX-SO
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32
封裝: 0.450 INCH, SOP-32
文件頁(yè)數(shù): 136/179頁(yè)
文件大?。?/td> 1070K
代理商: S3C70F2XX-SO
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)當(dāng)前第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
1-6
POWER-DOWN
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode; the STOP instruction initiates stop mode.
In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock
oscillation stops completely, halts all operations except for a few basic peripheral functions. A power-down is
terminated either by a
RESET or by an interrupt (with exception of the external interrupt INT0).
RESET
When
RESET is input during normal operation or during power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
I/O PORTS
The S3C70F2/C70F4 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FF6H
in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a
total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.
TIMERS and TIMER/COUNTER
The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer.
The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock
frequency.
The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and
dividing external clock signals. The 8-bit timer/counter generates a clock signal (
SCK) for the serial I/O interface.
The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit.
Its functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer
sound.
SERIAL I/O INTERFACE
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter
The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first
transmission is also selectable.
The serial interface can operate with an internal or an external clock source, or using the clock signal generated
by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO
mode register.
相關(guān)PDF資料
PDF描述
S3C70F4XX-AV 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30
S3C72M9XX-QA 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128
S3P72M9-QA 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128
S3C7414XX-AQ 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42
S3C7414XX-QZ 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S3C70F4 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange
S3C7235 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange
S3C7238 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange
S3C7281 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM, RAM.
S3C7295 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M