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參數(shù)資料
| 型號： | S3C70F2XX-SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
| 封裝： | 0.450 INCH, SOP-32 |
| 文件頁數(shù)： | 27/179頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S3C70F2XX-SO |
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TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
11-2
BASIC TIMER (BT)
OVERVIEW
The 8-bit basic timer (BT) has five functional components:
— Clock selector logic
— 4-bit mode register (BMOD)
— 8-bit counter register (BCNT)
— Watchdog timer control register (WDMOD)
— Watchdog timer clear flag (WDTCF)
The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.
You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize
clock oscillation when stop mode is released by an interrupt or
RESET.
Use the basic timer mode register, BMOD, to turn the BT on and off, to select input clock frequency, and to con-
trol interrupt or stabilization intervals.
Interval Timer Function
The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT
clock pulses.
To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the
interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2–BMOD.0.
The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the
frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs.
An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time
interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting
continues from 00H.
Watchdog Timer Function
The basic timer can also be used as a "watch-dog" timer to detects inadvertent program loop, that is, system or
program operation error. For this purpose, instruction that clears the watch-dog timer(BITS WDTCF) should be
executed at proper points in a program within a given period. If an instruction that clears the watch-dog timer is
not executed within the period and the watch-dog timer overflows, reset signal is generated and system is
restarted with reset status. An operation of watch-dog timer is as follows:
Write some value(except #5AH) to Watch-Dog Timer Mode register, WDMOD.
If WDCNT overflows, system reset is generated.
Oscillation Stabilization Interval Control
Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also
determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when
power-down mode is released by an interrupt. When a
RESET signal is generated, the standard stabilization
interval for system clock oscillation following a
RESET is 31.3 ms at 4.19 MHz.
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