
S3C70F2/C70F4/P70F4
INTERRUPTS
7-13
INTERRUPT MASTER ENABLE FLAG (IME)
The interrupt master enable flag, IME, inhibits or enables all interrupt processing. Therefore, even when an IRQx
flag and its corresponding IEx flag is enabled, an interrupt request will not be serviced until the IME flag is set to
logic one. The IME flag is the most significant bit of the 4-bit IPR register at RAM location FB2H.
IME
IPR.2
IPR.1
IPR.0
Effect of Bit Settings
0
Inhibit all interrupts
1
Enable all interrupts
You can manipulate the IME flag using EI and DI instructions, despite the current value of the enable memory
bank (EMB) flag.
INTERRUPT ENABLE FLAGS (IEx)
Interrupt enable flags are used to control the execution of service routines for specific interrupt requests. The
enable flag has priority over a request flag — even if the IRQx flag is enabled, the interrupt request will not be
serviced until the corresponding IEx flag is set to logic one.
Using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test IEx (and IRQx) flags despite
the current enable memory bank (EMB) value. The IEx and IRQx flags are mapped to RAM area FB8H–FBFH.
Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses
Address
Bit 3
Bit 2
Bit 1
Bit 0
FB8H
0
IEB
IRQB
FBAH
0
IEW
IRQW
FBBH
0
FBCH
0
IET0
IRQT0
FBDH
0
IES
IRQS
FBEH
IE1
IRQ1
IE0
IRQ0
FBFH
0
IEK
IRQK
NOTES:
1.
IEx refers generically to all interrupt enable flags.
2.
IRQx refers generically to all interrupt request flags.
3.
IEx = 0 is interrupt disable mode.
4.
IEx = 1 is interrupt enable mode.