參數(shù)資料
型號: S29PL129J
廠商: Spansion Inc.
英文描述: CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述: 3.0伏的CMOS只,同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶
文件頁數(shù): 87/106頁
文件大?。?/td> 1997K
代理商: S29PL129J
April 7, 200531107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
85
P R E L I M I N A R Y
Read Operations
Notes:
1. Not 100% tested.
2. See
Figure 9
and
Table 25
for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE#
high to the data bus driven to V
CC
/2 is taken as t
DF
.
4. S29PL129J has two CE# (CE1#, CE2#).
5. Valid CE1# / CE2# conditions: (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
) or (CE1# = V
IH,
CE2# = V
IH
)
6. Valid CE1# / CE2# transitions: (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
) to (CE1# = CE2# = V
IH
)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = V
IH
) to (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
)
8. For 70pF Output Load Capacitance, 2 ns will be added to the above t
ACC
,t
CE
,t
PACC
,t
OE
values for all speed grades
Table 27.
Read-Only Operations
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
55
60
65
70
Unit
t
AVAV
t
RC
Read Cycle Time (
Note 1
)
Min
55
60
65
70
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
55
60
65
70
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
55
60
65
70
ns
t
PACC
Page Access Time
Max
20
25
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
20
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (
Note 3
)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes
1
,
3
)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (
Note 3
)
Min
5
ns
t
OEH
Output Enable Hold
Time (
Note 1
)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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