參數(shù)資料
型號(hào)： S29PL129J
廠商： Spansion Inc.
英文描述： CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶
文件頁(yè)數(shù)： 27/106頁(yè)
文件大?。?/td> 1997K
代理商： S29PL129J
April 7, 200531107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
25
P R E L I M I N A R Y
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
SS
±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
READY
(during Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t
READY
(not during Embedded Al-
gorithms). The system can read data t
RH
after the RESET# pin returns to V
IH
.
Refer to the "
AC Characteristic
" section tables for RESET# parameters and to 13
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL129N 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FAI000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FAI002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FAI003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65FAIW00 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
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