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參數(shù)資料
| 型號(hào)： | S2061 |
| 廠(chǎng)商： | Applied Micro Circuits Corp. |
| 英文描述： | Serial Backplane Transceiver(用于高速串行數(shù)據(jù)傳送的收發(fā)器) |
| 中文描述： | 串行背板收發(fā)器（用于高速串行數(shù)據(jù)傳送的收發(fā)器） |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | S2061 |
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13
SERIAL BACKPLANE TRANSCEIVER
S2061
February 2, 1999 / Revision C
Parameters
Transmitter Output Jitter Allocation
Description
Min
Max
Units
Conditions
T
1
T
2
T
SDR ,
T
SDF
Data setup w.r.t. REFCLK
Data hold w.r.t. REFCLK
Serial data rise and fall
2
1.0
—
—
—
300
ns
ns
ps
See note.
—
20% to 80%, tested on a sample basis.
T
JRMS
Serial data output random
jitter (RMS)
—
20
ps
RMS, tested on a sample basis.
Measured with 1010 pattern.
Measured with K28.5
±
@ 1.25 GHz pattern.
—
80
ps
Peak-to-peak, tested on a sample basis.
Serial data output
deterministic jitter (p-p)
T
DJ
Table 13. S2061 Transmitter Timing
Table 14. S2061 Receiver Timing
Table 12. S2061 Performance Summary
Parameters
Description
Min
Max
Units
Conditions
T
3
T
4
T
5
T
6
T
7
T
RCR ,
T
RCF
T
DR ,
T
DF
T
SDR ,
T
SDF
T
LOCK
Duty Cycle
Input Jitter
Tolerance
RBC0 to RBC1 skew
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
RBC0, RBC1 rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RBC0/RBC1 Duty Cycle
Input data eye opening
allocation at receiver input
for BER
≤
1E–12
—
3.0
1.5
2.5
1.5
—
—
—
—
40%
30%
1
3.0
3.0
300
2.4
60%
—
ns
ns
ns
ns
ns
ns
ns
ps
μ
s
bit time
Tested on a sample basis.
1.0625 GHz Mode
1.0625 GHz Mode
1.250 GHz Mode
1.250 GHz Mode
Measured from .8V to 2.0V.
Measured from .8V to 2.0V.
20% to 80%. (See Figure 10.)
8B/10B IDLE pattern sample basis
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
r
c
n
d
d
e
k
e
m
u
q
e
F
o
p
k
o
p
m
i
n
c
o
e
a
r
a
g
P
1
6
0
2
S
s
U
s
s
M
n
n
n
H
M
*
y
e
n
p
l
S
e
B
o
q
c
A
e
R
O
0
0
0
0
5
0
2
1
8
0
2
2
1
1
5
6
1
4
9
4
5
2
2
0
1
0
1
c
k
o
o
s
s
s
c
1
0
5
0
0
c
n
5
z
h
w
d
W
*
±
10% lock range, nominal frequency is per FC-PH standard.
0
1
s
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
Note: All TTL/CMOS AC measurements are assumed to have the output load of 10pF.
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| S2064 | Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2061F | 制造商:PRX 功能描述:Silicon Controlled Rectifier, 50 Volt, 2.75A, TO-220 |
| S2061Y | 制造商:RCA 功能描述:Silicon Controlled Rectifier, 30 Volt, 2.75A, TO-220 |
| S2062TB | 制造商:AppliedMicro 功能描述:Backplane Transceiver 156-Pin TBGA |
| S2065A | 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA |
| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
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