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參數(shù)資料
| 型號(hào)： | S2061 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Serial Backplane Transceiver(用于高速串行數(shù)據(jù)傳送的收發(fā)器) |
| 中文描述： | 串行背板收發(fā)器（用于高速串行數(shù)據(jù)傳送的收發(fā)器） |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 142K |
| 代理商： | S2061 |
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1
SERIAL BACKPLANE TRANSCEIVER
S2061
S2061
February 2, 1999 / Revision C
DEVICE
SPECIFICATION
FEATURES
Transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
Receiver PLL configured for clock and data
recovery
1.0 – 1.25 Gbps operation
8-bit parallel TTL compatible interface
1.6W typical power dissipation
+3.3V power supply
Low-jitter serial PECL compatible interface
Lock detect
Local loopback
64 PQFP/TEP package
Framing performed by receiver
Continuous downstream clocking from receiver
Drives 30m of Twinax cable directly
APPLICATIONS
High-speed data communications
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
RAID drives
Mass storage devices
GENERAL DESCRIPTION
The S2061 transmitter and receiver chip is designed
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces. The chip runs
at data rates from 1.0 to 1.25 Gbps with associated
10-bit data word.
The chip performs parallel-to-serial and serial-to-par-
allel conversion, 8B/10B coding, and framing for
block-encoded data. The transmitter’s on-chip PLL
synthesizes the high-speed clock from a low-speed
reference. The receiver’s on-chip PLL synchronizes
directly to incoming digital signal to receive the data
stream. The transmitter and receiver each support
differential PECL-compatible I/O for fiber optic com-
ponent interfaces, to minimize crosstalk and maximize
data integrity. Local loopback mode is provided for
system diagnostics.
Figure 1 shows a typical configuration incorporating
the chip, which is compatible with AMCC’s Crosspoint
switch products.
Figure 1. System Block Diagram
Crosspoint
Switch
S2016(16x16)
S2025(32x32)
S2028(32x32)
MAC
MAC
1000 GBE
OC-3
OC-12
Fibre Channel
0
N
0
N
S2061
MAC
MAC
S2061
S2061
S2061
1000 GBE
OC-3
OC-12
Fibre Channel
1000 GBE
OC-3
OC-12
Fibre Channel
1000 GBE
OC-3
OC-12
Fibre Channel
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2062 | Dual Serial Backplane Transceiver(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的雙收發(fā)器) |
| S2064 | Quad Serial Backplane Device(用于以太網(wǎng)，光纖通道高速串行數(shù)據(jù)傳送的四收發(fā)器) |
| S2065 | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| S2066 | Quad GigaBit Ethernet Transceiver(四千兆位以太網(wǎng)收發(fā)器) |
| S2067 | Dual Serial Backplane Transceiver with Dual I/O(帶雙傳送接收串行I/O的雙收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2061F | 制造商:PRX 功能描述:Silicon Controlled Rectifier, 50 Volt, 2.75A, TO-220 |
| S2061Y | 制造商:RCA 功能描述:Silicon Controlled Rectifier, 30 Volt, 2.75A, TO-220 |
| S2062TB | 制造商:AppliedMicro 功能描述:Backplane Transceiver 156-Pin TBGA |
| S2065A | 制造商:AppliedMicro 功能描述:Backplane Transceiver 208-Pin TBGA |
| S2065J | 功能描述:SCR 65A 200V RoHS:否 制造商:STMicroelectronics 最大轉(zhuǎn)折電流 IBO:480 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:600 V 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:5 uA 開(kāi)啟狀態(tài) RMS 電流 (It RMS): 正向電壓下降:1.6 V 柵觸發(fā)電壓 (Vgt):1.3 V 最大柵極峰值反向電壓:5 V 柵觸發(fā)電流 (Igt):35 mA 保持電流（Ih 最大值）:75 mA 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-220 封裝:Tube |
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