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參數(shù)資料
| 型號(hào)： | S2004 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器） |
| 文件頁(yè)數(shù)： | 8/38頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | S2004 |
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8
QUAD SERIAL BACKPLANE DEVICE
S2004
October 10, 2000 / Revision D
In order to provide interface compatibility to non-
AMCC serial backplane transceivers, the S2004 can
also generate a unique sync character consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of SYNC and
DN. The SYNC character may start with either a
positive or negative parity K28.5. (Depending on the
current running disparity.) The parity of the second
and third K28.5 are inverse with respect to a valid
8B/10B sequence. Parity of the remaining K28.5 are
8B/10B compliant. Thus the parity of the K28.5 pat-
tern consists of + + - - + - + - + - + - + - + - or - - + + -
+ - + - + - + - + - +.
When operating in the channel locked mode, the
KGENx and DNx inputs must be driven for each
channel. The SYNC input is common to all four
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channels. Table 2 identifies the S2004 transmit con-
trol signals.
The special SYNC generation commences on the first
cycle in which SYNC and DN=1 and continues for 16
cycles. During this period, the SYNC, KGEN, and DN
inputs are ignored (assertion of DN and SYNC during
this period will not prolong or re-initialize the special
sync character generation).
Frequency Synthesizer (PLL)
The S2004 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2004 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Table 2. Transmitter Control Signals
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