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參數(shù)資料
| 型號： | S2004 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器） |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 377K |
| 代理商： | S2004 |
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15
S2004
QUAD SERIAL BACKPLANE DEVICE
October 10, 2000 / Revision D
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Table 8. Output Clock Mode (TMODE = 1)
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Table 8A. S2004 Data Clocking
When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 10. TCLKA is sourced from TCLKO, which
is frequency locked to the Reference clock input.
REFCLK
TCLKO
SerDes
TCLKA
REF
OSCILLATOR
Controller/MAC
ASIC/FPGA
PLL
Parallel Data
RCxP/N
2
Recovered
Clock
Figure 10. External Receiver Clocking
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