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參數(shù)資料
| 型號： | S2004 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器) |
| 中文描述： | 四串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的四串行收發(fā)器） |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 377K |
| 代理商： | S2004 |
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16
QUAD SERIAL BACKPLANE DEVICE
S2004
October 10, 2000 / Revision D
Figure 11. S2004 Diagnostic Loopback Operation
CRU
CSU
OTHER OPERATING MODES
Operating Frequency Range
The S2004 is designed to operate at serial baud
rates of .98 GHz to 1.3 GHz (800 Mbps to 1040
Mbps user data rate). The part is specified at Fibre
Channel (1062 MHz) and Gigabit Ethernet (1.25
GHz) serial baud rates, but will operate satisfactorily
at any rate in this range.
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver, as shown in Figure 11. This provides
the ability to perform system diagnostics and off-line
testing of the interface to verify the integrity of the
serial channel. Loopback mode is enabled indepen-
dently for each channel using its respective
loopback-enable input, LPEN.
TEST MODES
The S2004 has a testability input to aid in functional
testing of the device. The test mode is entered when
CH_LOCK is HIGH and TCLKB is HIGH. Thus users
must take care to insure that TCLKB is held LOW
when operating in the channel locked mode. The
following conditions are asserted when in test mode:
REFCLK replaces the VCO CLK (it also still
goes to the transmit clock mux).
TCLKA clocks all 4 transmit channels
TCLKC is muxed in as the lock detect REFCLK
for test purposes.
TCLKD High becomes the channel lock signal to
the whole of the chip except the transmit clock.
The RESET pin is used to initialize the Transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization). Note that Reset does not disable
the TCLKO output unless the TCLKB input is HIGH.
Note: Serial output data remains active during loopback opera-
tion to enable other system tests to be performed.
JTAG TESTING
The JTAG implementation for the S2004 is compli-
ant with the IEEE1149.1 requirements. JTAG is used
to test the connectivity of the pins on the chip. The
TAP, (Test Access Port), provides access to the test
logic of the chip. When TRST is asserted the TAP is
initialized. TAP is a state machine that is controlled
by TMS. The test instruction and data are loaded
through TDI on the rising edge of TCK. When TMS is
high the test instruction is loaded into the instruction
register. When TMS is low the test data is loaded
into the data register. TDO changes on the falling
edge of TCK. All input pins, including clocks, that
have boundary scan are observe only. They can be
sampled in either normal operational or test mode.
All output pins that have boundary scan, are observe
and control. They can be sampled as they are driven
out of the chip in normal operational mode, and they
can be driven out of the chip in test mode using the
Extest instruction. Since JTAG testing operates only
on digital signals there are some pins with analog
signals that JTAG does not cover. The JTAG imple-
mentation has the three required instruction, Bypass,
Extest, and Sample/Preload.
Instruction
BYPASS
EXTEST
SAMPLE/PRELOAD
ID CODE
Code
11
00
01
10
JTAG Instruction Description:
The BYPASS register contains a single shift-register
stage and is used to provide a minimum-length serial
path between the TDI and TDO pins of a component
when no test operation of that component is re-
quired. This allows more rapid movement of test
data to and from other components on a board that
are required to perform test operations.
The EXTEST instruction allows testing of off-chip cir-
cuitry and board level interconnections. Data would
typically be loaded onto the latched parallel outputs
of boundary-scan shift-register stages using the
SAMPLE/PRELOAD instruction prior to selection of
the EXTEST instruction.
The SAMPLE/PRELOAD instruction allows a snap-
shot of the normal operation of the component to be
taken and examined. It also allows data values to be
loaded onto the latched parallel outputs of the
boundary-scan shift register prior to selection of the
other boundary-scan test instructions.
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