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參數(shù)資料
| 型號(hào)： | S1C8F360F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | QFP18-176 |
| 文件頁(yè)數(shù)： | 53/217頁(yè) |
| 文件大?。?/td> | 1753K |
| 代理商： | S1C8F360F |
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136
EPSON
S1C8F360 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
SVDON: 00FF12HD4
Controls the turning ON/OFF of the continuous
sampling mode.
When "1" is written: Continuous sampling ON
When "0" is written: Continuous sampling OFF
When "1" is read:
BUSY
When "0" is read:
READY
The continuous sampling mode goes ON when "1"
is written to SVDON and goes OFF, when "0" is
written.
In the ON status, sampling of the supply voltage is
done continuously in 7.8 msec cycles and the
detection result is latched to SVD0–SVD3.
SVDON can be read, and "1" indicates SVD circuit
operation (BUSY) and "0" indicates standby
(READY).
At initial reset and in the SLEEP status, SVDON is
set to "0" (continuous sampling OFF/READY).
SVDSP: 00FF12HD5
Controls the turning ON/OFF of the 1/4 Hz auto-
sampling mode.
When "1" is written: Auto-sampling ON
When "0" is written: Auto-sampling OFF
Reading:
Valid
The 1/4 Hz auto-sampling mode goes ON when "1"
is written to SVDSP and goes OFF, when "0" is
written.
In the ON status, sampling is done in every 4
seconds and "1" is read from SVDON during the
actual sampling period (7.8 msec).
At initial reset and in the SLEEP status, SVDSP is
set to "0" (auto-sampling OFF).
SVD0–SVD3: 00FF12HD0–D3
The detection result of the SVD is set.
The reading data correspond to the detection levels
as shown in Table 5.16.4.2 and the data is main-
tained until the next sampling.
Table 5.16.4.2 Supply voltage detection results
SVD3
SVD0
Detection level
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
Level 0
SVD1
1
0
1
0
1
0
1
0
SVD2
1
0
1
0
For the correspondence between the detection level
and the supply voltage, see Chapter 10, "ELECTRI-
CAL CHARACTERISTICS".
The initial value at initial reset is set according to
the supply voltage detected at first sampling by
hardware. Data of this bit is undefined until this
sampling is completed.
5.16.4 Control of SVD circuit
Table 5.16.4.1 shows the SVD circuit control bits.
Table 5.16.4.1 SVD circuit control bits
Address Bit
Name
SR R/W
Function
Comment
10
00FF12 D7
D6
D5
D4
D3
D2
D1
D0
–
SVDSP
SVDON
SVD3
SVD2
SVD1
SVD0
–
SVD auto-sampling control
SVD continuous sampling control/status
SVD detection level
Constantry "0" when
being read
These registers are
reset to "0" when
SLP instruction is
executed.
*2
–
0
1
→0*1
0
X
R/W
R
–
On
Busy
On
–
Off
Ready
Off
R
W
SVD3
1
:
0
SVD2
1
:
0
SVD1
1
:
0
SVD0
1
0
:
0
Detection level
Level 15
Level 14
:
Level 0
*1 After initial reset, this status is set "1" until conclusion of hardware first sampling.
*2 Initial values are set according to the supply voltage detected at first sampling by hardware.
Until conclusion of first sampling, SVD0–SVD3 data are undefined.
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| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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