參數(shù)資料
型號(hào)： S1C8F360F
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
封裝： QFP18-176
文件頁(yè)數(shù)： 134/217頁(yè)
文件大?。?/td> 1753K
代理商： S1C8F360F
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S1C8F360 TECHNICAL MANUAL
EPSON
13
3 CPU AND BUS CONFIGURATION
In the single chip mode, these terminals are set as
output ports R30–R33.
Output
port
RD/WR
signal
R23
R24
RD
WR
64K
Bus mode
512K
(max.)
512K
(min.)
Bus mode
Single
chip
These two signals are only output when the
memory area of the external device is being
accessed. They are not output when internal
memory is accessed.
See Section 3.6.5, "WAIT control", for the output
timing of the signal.
Output
port
CE
signal
R30
R31
R32
R33
CE0
CE1
CE2
CE3
64K
512K
(max.)
512K
(min.)
Bus mode
Single
chip
_____
Fig. 3.6.4.1 Correspondence between CE signals
and output ports
The address range assigned to the four chip enable
_____
(CE) signals is determined by the bus mode setting.
In the expanded 64K mode, the four different
address ranges which match the amount of
memory in use can be selected in software.
Table 3.6.4.1 shows the address ranges which are
_____
assigned to the chip enable (CE) signal in each
mode. When accessing the internal memory area,
_____
the CE signal is not output. Care should be taken
here because the address range for these portions of
memory involves irregular settings.
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory.
Each of these signals is only output when the
memory area of the external device is being
accessed. They are not output when internal
memory is accessed.
Note: The CE signals will be inactive status when
the chip enters the standby mode (HALT
mode or SLEEP mode).
See Section 3.6.5, "WAIT control", for the output
timing of signal.
_____
Fig. 3.6.3.1 Correspondence between read (RD)/write
_____
(WR) signal and output ports
______
3.6.4 Chip enable (CE) signal
The S1C8F360 is equipped with address decoders
_____
which can output four different chip enable (CE)
signals.
Consequently, four devices equipped with a chip
_____
enable (CE) or chip select (CS) terminal can be
directly connected without setting the address
decoder to an external device.
_______ _______
The four chip enable (CE0–CE3) signal output
terminals and output circuits are shared with
output ports R30–R33 and in modes other than the
_____
single chip mode, the selection of chip enable (CE)
or output port can be set in software for each of the
_____
four bits. When set for chip enable (CE) output, the
data register and high impedance control register
for each output port are detached from the output
circuit and is usable as general purpose data
register with read/write capabilities.
Table 3.6.4.1 CE0–CE3 address settings
CE0
CE1
CE2
CE3
000000H–001FFFH
002000H–003FFFH
004000H–005FFFH
006000H–007FFFH
000000H–003FFFH
004000H–007FFFH
008000H–00BFFFH
00C000H–00EFFFH
000000H–007FFFH
008000H–00EFFFH
–
000000H–00EFFFH
–
8K bytes
16K bytes
32K bytes
64K bytes
Address range (selected in software)
CE signal
(1) Expanded 64K mode (MPU mode only)
CE0
CE1
CE2
CE3
200000H–27FFFFH
080000H–0FFFFFH
100000H–17FFFFH
180000H–1FFFFFH
000000H–00EFFFH, 010000H–07FFFFH
080000H–0FFFFFH
100000H–17FFFFH
180000H–1FFFFFH
Address range
CE signal
(2) Expanded 512K minimum/maximum modes
MCU mode
MPU mode
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