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參數(shù)資料
| 型號(hào)： | S1C8F360F |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | QFP18-176 |
| 文件頁(yè)數(shù)： | 101/217頁(yè) |
| 文件大?。?/td> | 1753K |
| 代理商： | S1C8F360F |
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S1C8F360 TECHNICAL MANUAL
EPSON
9
3 CPU AND BUS CONFIGURATION
3.5 Chip Mode
3.5.1 MCU mode and MPU mode
The chip operating mode can be set to one of two
_______
settings using the MCU/MPU terminal. The MCU/
_______
MPU terminal has a built-in pull-up resistor.
s
_______
MCU mode...Set the MCU/MPU terminal to HIGH
Switch to this setting when using internal
PROM. With respect to areas other than internal
memory, external memory can even be ex-
panded. See Section 3.5.2, "Bus mode", for the
memory map.
In the MCU mode, during initial reset, only
systems in internal memory are activated.
Internal PROM is normally fixed as the top
portion of the program memory from the
common area (logical space 0000H–7FFFH).
Exception processing vectors are assigned in
internal PROM. Furthermore, the application
initialization routines that start with reset
exception processing must likewise be written
to internal PROM. Since bus and other settings
which correlate with external expanded
memory can be executed in software, this
processing is executed in the initialization
routine written to internal PROM. Once these
bus mode settings are made, external memory
can be accessed.
When accessing internal memory in this mode,
_____
the chip enable (CE) and read (RD)/write (WR)
signals are not output to external memory, and
the data bus (D0–D7) goes into high impedance
status (pull-up status with the "pull-up resistors
for P00–P07.
Consequently, in cases where addresses overlap
in external and internal memory, the areas in
external memory will be unavailable.
s
_______
MPU mode...Set the MCU/MPU terminal to LOW
Internal PROM area is released to an external
device source. Internal PROM then becomes
unusable and when this area is accessed, chip
_____
enable (CE) and read (RD)/write (WR) signals
are output to external memory and the data bus
(D0–D7) become active. These signals are not
output to an external source when other areas of
internal memory are accessed.
When employing this mode, the exception
processing vectors and initialization routine
must be assigned within the common area
(000000H–007FFFH).
Note: Setting of MCU/MPU terminal is latched at
the rising edge of a reset signal input from
the RESET terminal. Therefore, if the setting
is to be changed, the RESET terminal must
be set to LOW level once again.
Table 3.3.1 Exception processing vector table
For each vector address and the address after it, the
start address of the exception processing routine is
written into the subordinate and super ordinate
sequence. When an exception processing factor is
generated, the exception processing routine is
executed starting from the recorded address.
When multiple exception processing factors are
generated at the same time, execution starts with
the highest priority item.
The priority sequence shown in Table 3.3.1 assumes
that the interrupt priority levels are all the same.
The interrupt priority levels can be set by software
in each system. (See Section 5.17 "Interrupt and
Standby Status".)
Note: For exception processing other than reset,
SC (system condition flag) and PC (program
counter) are evacuated to the stack and
branches to the exception processing
routines. Consequently, when returning to
the main routine from exception processing
routines, please use the RETE instruction.
See the "S1C88 Core CPU Manual" for information
on CPU operations when an exception processing
factor is generated.
3.4 CC (Customized Condition Flag)
The S1C8F360 does not use the customized condi-
tion flag (CC) in the core CPU. Accordingly, it
cannot be used as a branching condition for the
conditional branching instruction (JRS, CARS).
Vector
address
000000H
000002H
000004H
000006H
000008H
00000AH
00000CH
00000EH
000010H
000012H
000014H
000016H
000018H
00001AH
00001CH
00001EH
000020H
000022H
000024H
000026H
000028H
:
0000FEH
Priority
High
↑
↓
Low
No
priority
rating
Exception processing factor
Reset
Zero division
Watchdog timer (NMI)
Programmable timer 1 interrupt
Programmable timer 0 interrupt
K10, K11 input interrupt
K04–K07 input interrupt
K00–K03 input interrupt
Serial I/F error interrupt
Serial I/F receiving complete interrupt
Serial I/F transmitting complete interrupt
Stopwatch timer 100 Hz interrupt
Stopwatch timer 10 Hz interrupt
Stopwatch timer 1 Hz interrupt
Clock timer 32 Hz interrupt
Clock timer 8 Hz interrupt
Clock timer 2 Hz interrupt
Clock timer 1 Hz interrupt
A/D converter interrupt
System reserved (cannot be used)
Software interrupt
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| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F360F513200 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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| S1C-8-S | 制造商:GRIPCO 功能描述: |
| S1CFB | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLOORBOX, SYSTEM ONE, CAST IRON |
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