參數(shù)資料
型號(hào): S1C8F360F
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
封裝: QFP18-176
文件頁數(shù): 30/217頁
文件大?。?/td> 1753K
代理商: S1C8F360F
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S1C8F360 TECHNICAL MANUAL
EPSON
115
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller)
5.12.7 Display control
The display status of the built-in LCD driver and
the contrast adjustment can be controlled with the
built-in LCD controller. The LCD display status can
be selected by display control registers LCDC0 and
LCDC1. Setting the value and display status are
shown in Table 5.12.7.1.
Table 5.12.7.1 LCD display control
5.12.8 CL and FR outputs
In order for the S1C8F360 to handle connection to
an externally expanded LCD driver, output ports
R25 and R26 can be used to output a CL signal
(LCD synchronous signal) and FR signal (LCD
frame signal), respectively.
The configuration of output ports R25 and R26 are
shown in Figure 5.12.8.1.
LCDC1
LCDC0
LCD display
1
0
1
0
1
0
All LCDs lit (Static)
All LCDs out (Dynamic)
Normal display
Drive OFF
All the dots in the LCD display can be turned on or
off directly by the drive waveform output from the
LCD driver, and data in the display memory is not
changed. Also, since the common terminal at this
time is set to static drive when all the dots are on
and is set to dynamic drive when they are off, this
function can be used as follows:
(1) Since all dots on is binary output (VC5 and VSS)
with static drive, the common/segment termi-
nal can be used as a monitor terminal for the
OSC1 oscillation frequency adjustment.
(2) Since all dots off is dynamic drive, you can
brink the entire LCD display without changing
display memory data.
Selecting LCD drive OFF turns the LCD drive
power circuit OFF and all the VC1–VC5 terminals go
to VSS level. However, if external power supply has
been selected by the mask option, the VC1–VC5 shift
to floating status when drive is turned OFF.
Furthermore, when the SLP instruction is executed,
registers LCDC0 and LCDC1 are automatically
reset to "0" (set to drive off) by hardware.
The LCD contrast can be adjusted in 16 stages. This
adjustment is done by the contrast adjustment
register LC0–LC3, and the setting values corre-
spond to the contrast as shown in Table 5.12.7.2.
However, if external power supply has been
selected by the mask option, the contrast adjust-
ment register LC0–LC3 is ineffective and contrast
adjustment cannot be done.
Table 5.12.7.2 LCD contrast adjustment
LC3
LC0
Contrast
1
:
0
1
0
1
:
0
1
0
Dark
Light
LC1
1
0
:
1
0
LC2
1
:
0
Register R25D
Register LCCLK
R25 output
CL signal
Register R26D
Register LCFRM
R26 output
FR signal
Fig. 5.12.8.1 Configuration of R25 and R26
The output control for the CL signal is done by the
register LCCLK. When you set "1" for the LCCLK,
the CL signal is output from the output port
terminal R25, when "0" is set, the HIGH (VDD) level
is output. At this time, "1" must always be set for
the data register R25D.
The output control for the FR signal is done by the
register LCFRM. When you set "1" for the LCFRM,
the FR signal is output from the output port
terminal R26, when "0" is set, the HIGH (VDD) level
is output. At this time, "1" must always be set for
the data register R26D.
The frequencies of each signal are changed as
shown in Table 5.12.8.1 according to the drive duty
selection.
Table 5.12.8.1 Frequencies of CL and FR signals
Drive duty
1/32
1/16
1/8
CL signal (Hz)
2,048
1,024
FR signal (Hz)
32
64
Since the signals are generated asynchronously
from the registers LCCLK and LCFRM, when the
signals are turned ON or OFF by the register
settings, a hazard of a 1/2 cycle or less is generated.
Figure 5.12.8.2 shows the output waveforms of the
CL and FR signals.
Fig. 5.12.8.2 Output waveforms of CL and FR signals
(when 1/16 duty is selected)
Note: The CL and FR outputs are provided for
supporting the S1C883xx. When the TOUT
output (mask option for the S1C888xx) is
selected for R26, the CL and FR signals
cannot be output.
LCCLK/LCFRM
CL output (R25)
FR output (R26)
01
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