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參數(shù)資料
| 型號： | S-4544A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | LCD Controller-Driver With Built-in 8-Bit and Serial Interfaces(內(nèi)置8位和串行接口的LCD控制器-驅(qū)動器) |
| 中文描述： | LCD控制器與- 8內(nèi)置驅(qū)動器位和串行接口（內(nèi)置8位和串行接口的液晶顯示控制器-驅(qū)動器） |
| 文件頁數(shù)： | 23/39頁 |
| 文件大小： | 237K |
| 代理商： | S-4544A |
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LCD Controller-Driver
S-4544A
22
Seiko Instruments Inc.
6. Write Data
The 8-bit display data is written in the display data RAM. After writing the display data, the column address is
automatically incremented. To write the display data in succession after setting the 1st column address to be written
by the COLUMN ADDRESS SETTING command, the column address is not needed to be set each time. The icon
display data is valid for only D0.
7. Read Data
The 8-bit display data is read from the display data RAM. After the display data is read, the column address is
automatically incremented. To read the display data in succession after setting the 1st column address to be read by
the COLUMN ADDRESS SETTING command, the column address is not needed to be set each time. When reading
the display data immediately after setting the COLUMN ADDRESS SETTING, dummy read is needed once.
8. ADC Select
D0
:
0
Normal
Clockwise output. Column addresses 00H to 7FH correspond to segment outputs 1 to 128.
D0
:
1
Reverse
Counterclockwise output. Column addresses 00H to 7FH correspond to segment outputs 128 to 1.
Normal or reverse can be selected for the correlation between the column address of the display data RAM and the
segment output terminal. The ADC Select command selects normal or reverse in accordance with the relationship
between the column address of the display data RAM and the segment output. This minimizes restrictions in the
segment output wiring and IC assignment.
9. Display Normal/Reverse
D0
:
0
Normal
Display data
“
1
”
makes the display be lit
D0
:
1
Reverse
Display data
“
0
”
makes the display be lit
Lit or non-lit on each dot of the LCD panel can be reversed without rewriting the contents of the display data RAM.
The icon display is not reversed.
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
0
0
1
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
0
1
Write data in the display data RAM
Read data from the display data RAM
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