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參數(shù)資料
| 型號： | S-4544A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | LCD Controller-Driver With Built-in 8-Bit and Serial Interfaces(內(nèi)置8位和串行接口的LCD控制器-驅(qū)動器) |
| 中文描述： | LCD控制器與- 8內(nèi)置驅(qū)動器位和串行接口（內(nèi)置8位和串行接口的液晶顯示控制器-驅(qū)動器） |
| 文件頁數(shù)： | 22/39頁 |
| 文件大小： | 237K |
| 代理商： | S-4544A |
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LCD Controller-Driver
S-4544A
Seiko Instruments Inc.
21
4. Column Address Set
The column address is set when accessing the display data RAM from the MPU. When accessing the display data
RAM from the MPU, the column address is incremented. When accessing the successive column address from the
MPU, it is possible to access the display data without setting the column address each time. The automatic
increment stops at 7FH after accessing the top column address 7FH. The page address is not incremented.
While the Read Modify Write command is being executed, a set of Column Address Setting commands is neglected.
5. Status Read
D7
:
BUSY
=0 :
=1 :
Can accept a command.
Internal operation or reset state. Does not accept a command.
D6
:
ADC
=0 :
=1 :
ADC Reverse
ADC Normal
Make sure that this polarity is contrary to that of the ADC Select command.
D5
:
ON/OFF=0 :
Display ON
Display OFF
Make sure that this polarity is contrary to that of Display ON/OFF command.
=1 :
D4
:
RESET =0 :
Normal display operation state
Internal reset operation state with reset command.
=1 :
D3
:
PS
=0 :
=1 :
Normal display operation state
Power Save state
D2
:
MD
=0 :
=1 :
Normal display operation state
Icon only display state
D1
:
INVD
=0 :
=1 :
Display Normal
Display Reverse
D0
:
FDM
=0 :
=1 :
Normal display
Display All-Lit ON
During power-save, display ON/OFF, PS and FDM are individually output.
When selecting a parallel interface, the status read can also be executed during reset operation.
When a serial interface is selected, the status read is invalid during reset operation. However,
“
H
”
is output from the
SDO pin during reset operation.
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
Column Address:
Upper 3 bits
D1
D0
0
1
0
0
0
0
1
0
A6
A5
A4
0
1
0
0
0
0
0
A3
A2
A1
A0
A6
A5
A4
A3
A2
A1
A0
Column Address
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
H
1
H
7E
H
7F
H
A0
RDX
R/WX
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
Column Address:
Lower 4 bits
Ubi
Lower 4
bi
Status
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