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參數(shù)資料
| 型號： | S-4544A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | LCD Controller-Driver With Built-in 8-Bit and Serial Interfaces(內(nèi)置8位和串行接口的LCD控制器-驅(qū)動器) |
| 中文描述： | LCD控制器與- 8內(nèi)置驅(qū)動器位和串行接口（內(nèi)置8位和串行接口的液晶顯示控制器-驅(qū)動器） |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 237K |
| 代理商： | S-4544A |
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LCD Controller-Driver
S-4544A
12
Seiko Instruments Inc.
10. Page Address
The display RAM is composed of nine pages. When accessing the Display Data RAM from MPU, the page of the
Display Data RAM is set by a command.
11. Display Start Line Address
The display start line address is a read start address of the Display Data RAM which corresponds to the COM0
output. Set the display start line address with the corresponding command. Use the Display Start Line Address set
command in changing the display page or smooth scroll.
12. Reading the Display Data to LCD Panel
Regardless of the state of the MPU, the S-4544A reads the data to the LCD panel. That is, it reads a 1-line of the
display data specified with the line address from the Display Data RAM to the display data latch in the display drive
side. After reading 1-line address, the S-4544A increments the line address in synchronization with the common
output. After reading 1-frame line address, the S-4544A reads the display data from the display start line address
again.
13. Display Data Latch
The display data latch is the circuit for latching one line
’
s display data from the Display Data RAM. The display data
is output from this latch to the LCD drive circuit. Since the display ON/OFF, the display All-Lit ON/OFF and Display
Normal/Reverse control the display data latch, it has no effect on the display RAM data.
14. CR Oscillation Circuit
A built-in CR oscillation circuit generates a fundamental clock which conforms to the display timing. The oscillating
frequency
“
fosc
”
is approximately 18 kHz, when Rf=1 M
. Operation through external clock is possible when
external clock is input to OSC1, and OSC2 is
“
Open
”
15. LCD Drive Circuit
Has LCD drive output pins (i.e., 32 for common output, 2 for icon common, and 128 for segment output) and
generates a 2-frame AC drive waveform (type B). 2 icon common output pins which are configured oppositely to the
chip generate a drive waveform at the same timing. The icon display can be assigned the top or the bottom of the
LCD panel. When the icon display is in no use, turn the icon common output to “Open.”
16. LCD Power Supply Circuit
The LCD power supply circuit consists of a doubler/tripler, an LCD voltage adjustment circuit, an LCD bias resistor,
and a voltage follower. The LCD voltage adjustment circuit consists of a voltage regulator and an LCD voltage
command fine adjustment circuit. The LCD power supply circuit can be controlled by pins FNC1 and 2 and the LCD
power supply circuit ON/OFF command. Internal or external power supply for the doubler/tripler, voltage regulator,
and LCD voltage adjustment circuit can be changed with pins FNC1 and 2.
When turning OFF the LCD power supply circuit with the ON/OFF command, the S-4544A can stop the LCD power
supply circuit.
When turning OFF all of built-in LCD power supply circuits with FNC1 = “L,” FNC2 = “H,” the LCD power supply
circuit, however, can run at LCD bias voltage V1 through V5 generated by external bias resistors.
Page D3
0
1
2
3
4
5
6
7
8
D2
0
0
0
0
0
0
0
0
1
D1
0
0
0
0
1
1
1
1
0
D0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Graphic display area
Graphic display area
Graphic display area
Graphic display area
Graphic display area
Graphic display area
Graphic display area
Graphic display area
Icon (annunciator) display area
Frame Frequency
66.17 Hz
68.18 Hz
1
/17 duty
1/33 duty
at fosc = 18 kHz
at fosc = 18 kHz
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